From f1d86a931b2c51a24540e7ea3cda60dc154e064a Mon Sep 17 00:00:00 2001 From: Ulrich Drepper Date: Fri, 5 May 2000 16:49:44 +0000 Subject: Update. 2000-05-05 Jes Sorensen * sysdeps/unix/sysv/linux/ia64/sysdep.h: New file. * sysdeps/unix/sysv/linux/ia64/syscall.S: New file. * sysdeps/unix/sysv/linux/ia64/bits/types.h: New file. * sysdeps/unix/sysv/linux/ia64/bits/endian.h: New file. * sysdeps/ia64/Implies: New file. * sysdeps/ia64/Versions: New file. Declare _dl_symbol_address. * sysdeps/ia64/Makefile: New file. * sysdeps/ia64/gmp-mparam.h: New file, * sysdeps/ia64/elf/start.S: New file. * sysdeps/ia64/bits/fenv.h: New file. 2000-05-05 David Mosberger-Tang * sysdeps/unix/sysv/linux/ia64/sysdep.S: New file. 2000-04-26 Jes Sorensen * sysdeps/unix/sysv/linux/ia64/bits/elfclass.h: New file. The ia64 has 64 bit .hash entries just as the Alpha. 2000-04-25 Jes Sorensen * sysdeps/ia64/memprof.h: New file. Provide GETSP() macro. 2000-04-17 Jes Sorensen * sysdeps/ia64/fpu/fclrexcpt.c: New file. * sysdeps/ia64/fpu/fedisblxcpt.c: New file. * sysdeps/ia64/fpu/feenablxcpt.c: New file. * sysdeps/ia64/fpu/fegetenv.c: New file. * sysdeps/ia64/fpu/fegetexcept.c: New file. * sysdeps/ia64/fpu/fegetround.c: New file. * sysdeps/ia64/fpu/feholdexcpt.c: New file. * sysdeps/ia64/fpu/fesetenv.c: New file. * sysdeps/ia64/fpu/fesetround.c: New file. * sysdeps/ia64/fpu/feupdateenv.c: New file. * sysdeps/ia64/fpu/fgetexcptflg.c: New file. * sysdeps/ia64/fpu/fraiseexcpt.c: New file. * sysdeps/ia64/fpu/fsetexcptflg.c: New file. * sysdeps/ia64/fpu/ftestexcept.c: New file. * sysdeps/unix/sysv/linux/i386/dl-procinfo.h (_DL_HWCAP_COUNT): New. * sysdeps/unix/sysv/linux/sparc/sparc32/dl-procinfo.h (_DL_HWCAP_COUNT): New. * sysdeps/unix/sysv/linux/sparc/sparc64/dl-procinfo.h (_DL_HWCAP_COUNT): New. --- sysdeps/ia64/fpu/fraiseexcpt.c | 94 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) create mode 100644 sysdeps/ia64/fpu/fraiseexcpt.c (limited to 'sysdeps/ia64/fpu/fraiseexcpt.c') diff --git a/sysdeps/ia64/fpu/fraiseexcpt.c b/sysdeps/ia64/fpu/fraiseexcpt.c new file mode 100644 index 0000000000..78a881117e --- /dev/null +++ b/sysdeps/ia64/fpu/fraiseexcpt.c @@ -0,0 +1,94 @@ +/* Raise given exceptions. + Copyright (C) 1997, 1998, 2000 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jes Sorensen , 2000. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Library General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Library General Public License for more details. + + You should have received a copy of the GNU Library General Public + License along with the GNU C Library; see the file COPYING.LIB. If not, + write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include +#include +#include +#include +#include + +int +feraiseexcept (int excepts) +{ + fenv_t fpsr; + double tmp; + double dummy; + + /* Raise exceptions represented by EXPECTS. But we must raise only + one signal at a time. It is important the if the overflow/underflow + exception and the inexact exception are given at the same time, + the overflow/underflow exception precedes the inexact exception. */ + + /* We do these bits in assembly to be certain GCC doesn't optimize + away something important. */ + + /* First: invalid exception. */ + if (FE_INVALID & excepts) + { + /* One example of a invalid operation is 0 * Infinity. */ + tmp = 0; + __asm__ __volatile__ ("frcpa.s0 %0,p1=f0,f0" : "=f" (tmp) : : "p1" ); + } + + /* Next: division by zero. */ + if (FE_DIVBYZERO & excepts) + __asm__ __volatile__ ("frcpa.s0 %0,p1=f1,f0" : "=f" (tmp) : : "p1" ); + + /* XXX There seem to be no reliable way to generate + overflow/underflow exceptions without causing inexact exceptions + as well. */ + /* Next: overflow. */ + if (FE_OVERFLOW & excepts) + { + __asm__ __volatile__ ("mov.m %0=ar.fpsr" : "=r" (fpsr)); + fpsr |= (FE_OVERFLOW << 13); + __asm__ __volatile__ ("mov.m ar.fpsr=%0" : : "r" (fpsr)); + + if (!((unsigned long int) fpsr & FE_OVERFLOW)) + { + pid_t pid = getpid (); + kill (pid, SIGFPE); + } + } + + /* Next: underflow. */ + if (FE_UNDERFLOW & excepts) + { + __asm__ __volatile__ ("mov.m %0=ar.fpsr" : "=r" (fpsr)); + fpsr |= (FE_UNDERFLOW << 13); + __asm__ __volatile__ ("mov.m ar.fpsr=%0" : : "r" (fpsr)); + + if (!((unsigned long int) fpsr & FE_UNDERFLOW)) + { + pid_t pid = getpid(); + kill (pid, SIGFPE); + } + } + + /* Last: inexact. */ + if (FE_INEXACT & excepts) + { + dummy = DBL_MAX; + __asm__ __volatile__ ("fadd.d.s0 %0=%1,f1" : "=f" (dummy) : "0" (dummy)); + } + + /* Success. */ + return 0; +} -- cgit 1.4.1