From 2510d01ddba195f8cfaa3c2349f75e0612719d82 Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <hongjiu.lu@intel.com>
Date: Sun, 13 Dec 2009 15:23:02 -0800
Subject: Define bit_SSE2 and index_SSE2.

---
 sysdeps/i386/i686/multiarch/strcspn.S | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'sysdeps/i386/i686/multiarch/strcspn.S')

diff --git a/sysdeps/i386/i686/multiarch/strcspn.S b/sysdeps/i386/i686/multiarch/strcspn.S
index 73e7eb45a8..b2310e4a8b 100644
--- a/sysdeps/i386/i686/multiarch/strcspn.S
+++ b/sysdeps/i386/i686/multiarch/strcspn.S
@@ -23,7 +23,7 @@
 #ifdef HAVE_SSE4_SUPPORT
 
 #include <sysdep.h>
-#include <ifunc-defines.h>
+#include <init-arch.h>
 
 #ifdef USE_AS_STRPBRK
 #define STRCSPN_SSE42	__strpbrk_sse42
@@ -64,7 +64,7 @@ ENTRY(STRCSPN)
 	jne	1f
 	call	__init_cpu_features
 1:	leal	STRCSPN_IA32@GOTOFF(%ebx), %eax
-	testl	$(1<<20), CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET+__cpu_features@GOTOFF(%ebx)
+	testl	$bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx)
 	jz	2f
 	leal	STRCSPN_SSE42@GOTOFF(%ebx), %eax
 2:	popl	%ebx
@@ -80,7 +80,7 @@ ENTRY(STRCSPN)
 	jne	1f
 	call	__init_cpu_features
 1:	leal	STRCSPN_IA32, %eax
-	testl	$(1<<20), CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET+__cpu_features
+	testl	$bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features
 	jz	2f
 	leal	STRCSPN_SSE42, %eax
 2:	ret
-- 
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