From 78c01a5cbeb6717ffa2d4d66bb90ac5c39bd81a9 Mon Sep 17 00:00:00 2001 From: Joe Ramsay Date: Wed, 28 Jun 2023 12:19:38 +0100 Subject: aarch64: Add vector implementations of log routines Optimised implementations for single and double precision, Advanced SIMD and SVE, copied from Arm Optimized Routines. Log lookup table added as HIDDEN symbol to allow it to be shared between AdvSIMD and SVE variants. As previously, data tables are used via a barrier to prevent overly aggressive constant inlining. Special-case handlers are marked NOINLINE to avoid incurring the penalty of switching call standards unnecessarily. Reviewed-by: Szabolcs Nagy --- sysdeps/aarch64/fpu/vecmath_config.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'sysdeps/aarch64/fpu/vecmath_config.h') diff --git a/sysdeps/aarch64/fpu/vecmath_config.h b/sysdeps/aarch64/fpu/vecmath_config.h index d0bdbb4ae8..0920658a0c 100644 --- a/sysdeps/aarch64/fpu/vecmath_config.h +++ b/sysdeps/aarch64/fpu/vecmath_config.h @@ -35,4 +35,14 @@ __ptr; \ }) +#define V_LOG_POLY_ORDER 6 +#define V_LOG_TABLE_BITS 7 +extern const struct v_log_data +{ + /* Shared data for vector log and log-derived routines (e.g. asinh). */ + double poly[V_LOG_POLY_ORDER - 1]; + double ln2; + double invc[1 << V_LOG_TABLE_BITS]; + double logc[1 << V_LOG_TABLE_BITS]; +} __v_log_data attribute_hidden; #endif -- cgit 1.4.1