From a8e3ab3074d448ff3e58ac8f850d955dfed830ad Mon Sep 17 00:00:00 2001 From: Joe Ramsay Date: Thu, 5 Oct 2023 17:10:50 +0100 Subject: aarch64: Add vector implementations of log2 routines A table is also added, which is shared between AdvSIMD and SVE log2. --- sysdeps/aarch64/fpu/test-float-sve-wrappers.c | 1 + 1 file changed, 1 insertion(+) (limited to 'sysdeps/aarch64/fpu/test-float-sve-wrappers.c') diff --git a/sysdeps/aarch64/fpu/test-float-sve-wrappers.c b/sysdeps/aarch64/fpu/test-float-sve-wrappers.c index fa41ce09d8..f5e9584265 100644 --- a/sysdeps/aarch64/fpu/test-float-sve-wrappers.c +++ b/sysdeps/aarch64/fpu/test-float-sve-wrappers.c @@ -36,5 +36,6 @@ SVE_VECTOR_WRAPPER (cosf_sve, _ZGVsMxv_cosf) SVE_VECTOR_WRAPPER (expf_sve, _ZGVsMxv_expf) SVE_VECTOR_WRAPPER (exp2f_sve, _ZGVsMxv_exp2f) SVE_VECTOR_WRAPPER (logf_sve, _ZGVsMxv_logf) +SVE_VECTOR_WRAPPER (log2f_sve, _ZGVsMxv_log2f) SVE_VECTOR_WRAPPER (sinf_sve, _ZGVsMxv_sinf) SVE_VECTOR_WRAPPER (tanf_sve, _ZGVsMxv_tanf) -- cgit 1.4.1