From 3bb1af20513b8b70b8d404c71fb0956f00f8bf6b Mon Sep 17 00:00:00 2001 From: Joe Ramsay Date: Wed, 28 Jun 2023 12:19:37 +0100 Subject: aarch64: Add vector implementations of sin routines Optimised implementations for single and double precision, Advanced SIMD and SVE, copied from Arm Optimized Routines. As previously, data tables are used via a barrier to prevent overly aggressive constant inlining. Special-case handlers are marked NOINLINE to avoid incurring the penalty of switching call standards unnecessarily. Reviewed-by: Szabolcs Nagy --- sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c | 1 + 1 file changed, 1 insertion(+) (limited to 'sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c') diff --git a/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c b/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c index cb45fd3298..4af97a25a2 100644 --- a/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c +++ b/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c @@ -24,3 +24,4 @@ #define VEC_TYPE float64x2_t VPCS_VECTOR_WRAPPER (cos_advsimd, _ZGVnN2v_cos) +VPCS_VECTOR_WRAPPER (sin_advsimd, _ZGVnN2v_sin) -- cgit 1.4.1