From 4a9392ffc27ad280f84779eea3ba01f2c134d1d8 Mon Sep 17 00:00:00 2001 From: Joe Ramsay Date: Wed, 28 Jun 2023 12:19:39 +0100 Subject: aarch64: Add vector implementations of exp routines Optimised implementations for single and double precision, Advanced SIMD and SVE, copied from Arm Optimized Routines. As previously, data tables are used via a barrier to prevent overly aggressive constant inlining. Special-case handlers are marked NOINLINE to avoid incurring the penalty of switching call standards unnecessarily. Reviewed-by: Szabolcs Nagy --- sysdeps/aarch64/fpu/Makefile | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'sysdeps/aarch64/fpu/Makefile') diff --git a/sysdeps/aarch64/fpu/Makefile b/sysdeps/aarch64/fpu/Makefile index cc90c4cb75..04aa2e37ca 100644 --- a/sysdeps/aarch64/fpu/Makefile +++ b/sysdeps/aarch64/fpu/Makefile @@ -1,4 +1,5 @@ libmvec-supported-funcs = cos \ + exp \ log \ sin @@ -12,7 +13,8 @@ libmvec-support = $(addsuffix f_advsimd,$(float-advsimd-funcs)) \ $(addsuffix _advsimd,$(double-advsimd-funcs)) \ $(addsuffix f_sve,$(float-sve-funcs)) \ $(addsuffix _sve,$(double-sve-funcs)) \ - v_log_data + v_log_data \ + v_exp_data endif sve-cflags = -march=armv8-a+sve -- cgit 1.4.1