From e3e3eb0a2ea615c272cec5f47ba9f243ccdaf386 Mon Sep 17 00:00:00 2001 From: Adhemerval Zanella Date: Tue, 22 Jun 2021 16:41:28 -0300 Subject: x86: Fix tst-cpu-features-cpuinfo on Ryzen 9 (BZ #27873) AMD define different flags for IRPB, IBRS, and STIPBP [1], so new x86_64_cpu are added and IBRS_IBPB is only tested for Intel. The SSDB is also defined and implemented different on AMD [2], and also a new AMD_SSDB flag is added. It should map to the cpuinfo 'ssdb' on recent AMD cpus. It fixes tst-cpu-features-cpuinfo and tst-cpu-features-cpuinfo-static on recent AMD cpus. Checked on x86_64-linux-gnu on AMD Ryzen 9 5900X. [1] https://developer.amd.com/wp-content/resources/Architecture_Guidelines_Update_Indirect_Branch_Control.pdf [2] https://bugzilla.kernel.org/show_bug.cgi?id=199889 Reviewed-by: H.J. Lu --- manual/platform.texi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'manual') diff --git a/manual/platform.texi b/manual/platform.texi index a0b204b099..4cd029cfad 100644 --- a/manual/platform.texi +++ b/manual/platform.texi @@ -177,6 +177,18 @@ The supported processor features are: @item @code{AESKLE} -- AES Key Locker instructions are enabled by OS. +@item +@code{AMD_IBPB} -- Indirect branch predictor barrier (IBPB) for AMD cpus. + +@item +@code{AMD_IBRS} -- Indirect branch restricted speculation (IBPB) for AMD cpus. + +@item +@code{AMD_SSBD} -- Speculative Store Bypass Disable (SSBD) for AMD cpus. + +@item +@code{AMD_STIBP} -- Single thread indirect branch predictors (STIBP) for AMD cpus. + @item @code{AMX_BF16} -- Tile computational operations on bfloat16 numbers. -- cgit 1.4.1