From 2572f356b18ddee03b331ba33f5a2ae65d031a59 Mon Sep 17 00:00:00 2001 From: Rajalakshmi Srinivasaraghavan Date: Mon, 3 Jul 2017 10:46:13 +0530 Subject: powerpc: Clean up strlen and strnlen for power8 To align a quadword aligned address to 64 bytes, maximum of three 16 bytes load is needed for worst case instead of loading four times. --- ChangeLog | 5 +++++ sysdeps/powerpc/powerpc64/power8/strlen.S | 11 ----------- sysdeps/powerpc/powerpc64/power8/strnlen.S | 10 +--------- 3 files changed, 6 insertions(+), 20 deletions(-) diff --git a/ChangeLog b/ChangeLog index 4cd5d31770..9697355c79 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,8 @@ +2017-07-03 Rajalakshmi Srinivasaraghavan + + * sysdeps/powerpc/powerpc64/power8/strlen.S: Remove unreachable code. + * sysdeps/powerpc/powerpc64/power8/strnlen.S: Likewise. + 2017-07-01 Florian Weimer H.J. Lu diff --git a/sysdeps/powerpc/powerpc64/power8/strlen.S b/sysdeps/powerpc/powerpc64/power8/strlen.S index 8fdb6f5cc1..5691d1d93a 100644 --- a/sysdeps/powerpc/powerpc64/power8/strlen.S +++ b/sysdeps/powerpc/powerpc64/power8/strlen.S @@ -135,17 +135,6 @@ L(align64): addi r9,r9,16 bne cr7,L(dword_zero) - andi. r10,r9,63 - beq cr0,L(preloop) - ld r6,8(r4) - ldu r5,16(r4) - cmpb r10,r6,r0 - cmpb r11,r5,r0 - or r5,r10,r11 - cmpdi cr7,r5,0 - addi r9,r9,16 - bne cr7,L(dword_zero) - andi. r10,r9,63 beq cr0,L(preloop) ld r6,8(r4) diff --git a/sysdeps/powerpc/powerpc64/power8/strnlen.S b/sysdeps/powerpc/powerpc64/power8/strnlen.S index 07608ffa26..6d669d4a54 100644 --- a/sysdeps/powerpc/powerpc64/power8/strnlen.S +++ b/sysdeps/powerpc/powerpc64/power8/strnlen.S @@ -141,15 +141,7 @@ ENTRY_TOCLESS (__strnlen) addi r4,r4,-16 /* Decrement maxlen in 16 bytes. */ bne cr6,L(found_aligning64B) /* If found null bytes. */ - /* Unroll 3x above code block until aligned or find null bytes. */ - andi. r7,r5,63 - beq cr0,L(preloop_64B) - lvx v1,r5,r6 - vcmpequb. v1,v1,v0 - addi r5,r5,16 - addi r4,r4,-16 - bne cr6,L(found_aligning64B) - + /* Unroll 2x above code block until aligned or find null bytes. */ andi. r7,r5,63 beq cr0,L(preloop_64B) lvx v1,r5,r6 -- cgit 1.4.1