From 0b25c28e028b63c95108c442d8112811107e4c13 Mon Sep 17 00:00:00 2001 From: Paul Pluzhnikov Date: Tue, 23 May 2023 12:11:30 +0000 Subject: Fix misspellings in sysdeps/powerpc -- BZ 25337 All fixes are in comments, so the binaries should be identical before/after this commit, but I can't verify this. Reviewed-by: Rajalakshmi Srinivasaraghavan --- sysdeps/powerpc/atomic-machine.h | 2 +- sysdeps/powerpc/bits/setjmp.h | 2 +- sysdeps/powerpc/powerpc32/405/memcpy.S | 4 ++-- sysdeps/powerpc/powerpc32/405/memset.S | 10 +++++----- sysdeps/powerpc/powerpc32/476/memset.S | 10 +++++----- sysdeps/powerpc/powerpc32/power4/multiarch/strncase-power7.c | 2 +- sysdeps/powerpc/powerpc32/power4/multiarch/strncase_l-power7.c | 2 +- sysdeps/powerpc/powerpc64/configure.ac | 2 +- .../le/fpu/multiarch/float128-ifunc-redirect-macros.h | 2 +- sysdeps/powerpc/powerpc64/le/fpu/multiarch/float128-ifunc.h | 2 +- sysdeps/powerpc/powerpc64/le/fpu/multiarch/float128_private.h | 2 +- sysdeps/powerpc/powerpc64/power7/memmove.S | 2 +- sysdeps/powerpc/powerpc64/power7/strcmp.S | 2 +- sysdeps/powerpc/powerpc64/power7/strncpy.S | 2 +- sysdeps/powerpc/powerpc64/power7/strrchr.S | 2 +- sysdeps/powerpc/powerpc64/power8/strcasestr.S | 4 ++-- sysdeps/powerpc/powerpc64/power8/strcmp.S | 2 +- sysdeps/powerpc/powerpc64/power8/strlen.S | 2 +- sysdeps/powerpc/powerpc64/power8/strncmp.S | 2 +- sysdeps/powerpc/powerpc64/power8/strncpy.S | 4 ++-- sysdeps/powerpc/powerpc64/power8/strnlen.S | 2 +- sysdeps/powerpc/powerpc64/power8/strrchr.S | 2 +- sysdeps/powerpc/powerpc64/setjmp-bug21895.c | 2 +- 23 files changed, 34 insertions(+), 34 deletions(-) diff --git a/sysdeps/powerpc/atomic-machine.h b/sysdeps/powerpc/atomic-machine.h index aae467cc50..80369e0f94 100644 --- a/sysdeps/powerpc/atomic-machine.h +++ b/sysdeps/powerpc/atomic-machine.h @@ -18,7 +18,7 @@ /* * Never include sysdeps/powerpc/atomic-machine.h directly. - * Alway use include/atomic.h which will include either + * Always use include/atomic.h which will include either * sysdeps/powerpc/powerpc32/atomic-machine.h * or * sysdeps/powerpc/powerpc64/atomic-machine.h diff --git a/sysdeps/powerpc/bits/setjmp.h b/sysdeps/powerpc/bits/setjmp.h index ac92616ec9..201208a53a 100644 --- a/sysdeps/powerpc/bits/setjmp.h +++ b/sysdeps/powerpc/bits/setjmp.h @@ -32,7 +32,7 @@ /* The current powerpc 32-bit Altivec ABI specifies for SVR4 ABI and EABI the vrsave must be at byte 248 & v20 at byte 256. So we must pad this - correctly on 32 bit. It also insists that vecregs are only gauranteed + correctly on 32 bit. It also insists that vecregs are only guaranteed 4 byte alignment so we need to use vperm in the setjmp/longjmp routines. We have to version the code because members like int __mask_was_saved in the jmp_buf will move as jmp_buf is now larger than 248 bytes. We diff --git a/sysdeps/powerpc/powerpc32/405/memcpy.S b/sysdeps/powerpc/powerpc32/405/memcpy.S index a2d0df0e32..b5db693142 100644 --- a/sysdeps/powerpc/powerpc32/405/memcpy.S +++ b/sysdeps/powerpc/powerpc32/405/memcpy.S @@ -26,10 +26,10 @@ r5:byte count Save return address in r0. - If destinationn and source are unaligned and copy count is greater than 256 + If destination and source are unaligned and copy count is greater than 256 then copy 0-3 bytes to make destination aligned. If 32 or more bytes to copy we use 32 byte copy loop. - Finaly we copy 0-31 extra bytes. */ + Finally we copy 0-31 extra bytes. */ EALIGN (memcpy, 5, 0) /* Check if bytes to copy are greater than 256 and if diff --git a/sysdeps/powerpc/powerpc32/405/memset.S b/sysdeps/powerpc/powerpc32/405/memset.S index 6c574ed79e..8ddad2274c 100644 --- a/sysdeps/powerpc/powerpc32/405/memset.S +++ b/sysdeps/powerpc/powerpc32/405/memset.S @@ -27,13 +27,13 @@ r12:temp return address Save return address in r12 - If destinationn is unaligned and count is greater tha 255 bytes + If destination is unaligned and count is greater than 255 bytes set 0-3 bytes to make destination aligned - If count is greater tha 255 bytes and setting zero to memory - use dbcz to set memeory when we can - otherwsie do the follwoing + If count is greater than 255 bytes and setting zero to memory + use dbcz to set memory when we can + otherwise do the following If 16 or more words to set we use 16 word copy loop. - Finaly we set 0-15 extra bytes with string store. */ + Finally we set 0-15 extra bytes with string store. */ EALIGN (memset, 5, 0) rlwinm r11,r4,0,24,31 diff --git a/sysdeps/powerpc/powerpc32/476/memset.S b/sysdeps/powerpc/powerpc32/476/memset.S index 527291e1b9..29b0feaccc 100644 --- a/sysdeps/powerpc/powerpc32/476/memset.S +++ b/sysdeps/powerpc/powerpc32/476/memset.S @@ -27,13 +27,13 @@ r12:temp return address Save return address in r12 - If destinationn is unaligned and count is greater tha 255 bytes + If destination is unaligned and count is greater than 255 bytes set 0-3 bytes to make destination aligned - If count is greater tha 255 bytes and setting zero to memory - use dbcz to set memeory when we can - otherwsie do the follwoing + If count is greater than 255 bytes and setting zero to memory + use dbcz to set memory when we can + otherwise do the following If 16 or more words to set we use 16 word copy loop. - Finaly we set 0-15 extra bytes with string store. */ + Finally we set 0-15 extra bytes with string store. */ EALIGN (memset, 5, 0) rlwinm r11,r4,0,24,31 diff --git a/sysdeps/powerpc/powerpc32/power4/multiarch/strncase-power7.c b/sysdeps/powerpc/powerpc32/power4/multiarch/strncase-power7.c index 4c144ac620..d5602fca6a 100644 --- a/sysdeps/powerpc/powerpc32/power4/multiarch/strncase-power7.c +++ b/sysdeps/powerpc/powerpc32/power4/multiarch/strncase-power7.c @@ -1,4 +1,4 @@ -/* Optimized strcasecmp_l implememtation for POWER7. +/* Optimized strcasecmp_l implementation for POWER7. Copyright (C) 2013-2023 Free Software Foundation, Inc. This file is part of the GNU C Library. diff --git a/sysdeps/powerpc/powerpc32/power4/multiarch/strncase_l-power7.c b/sysdeps/powerpc/powerpc32/power4/multiarch/strncase_l-power7.c index fb668a1f34..477b8e72cf 100644 --- a/sysdeps/powerpc/powerpc32/power4/multiarch/strncase_l-power7.c +++ b/sysdeps/powerpc/powerpc32/power4/multiarch/strncase_l-power7.c @@ -1,4 +1,4 @@ -/* Optimized strcasecmp_l implememtation for POWER7. +/* Optimized strcasecmp_l implementation for POWER7. Copyright (C) 2013-2023 Free Software Foundation, Inc. This file is part of the GNU C Library. diff --git a/sysdeps/powerpc/powerpc64/configure.ac b/sysdeps/powerpc/powerpc64/configure.ac index 111a0ae4b3..575745af3e 100644 --- a/sysdeps/powerpc/powerpc64/configure.ac +++ b/sysdeps/powerpc/powerpc64/configure.ac @@ -27,7 +27,7 @@ fi # We check if compiler supports @notoc generation since there is no # gain by enabling it if it will be optimized away by the linker. # It also helps linkers that might not optimize it and end up -# generating stubs with ISA 3.1 instruction even targetting older ISA. +# generating stubs with ISA 3.1 instruction even targeting older ISA. AC_CACHE_CHECK([if the compiler supports @notoc], libc_cv_ppc64_notoc, [dnl cat > conftest.c < -/* Declare these now. These prototyes are not included +/* Declare these now. These prototypes are not included in any header. */ extern __typeof (cosf128) __ieee754_cosf128; extern __typeof (asinhf128) __ieee754_asinhf128; diff --git a/sysdeps/powerpc/powerpc64/power7/memmove.S b/sysdeps/powerpc/powerpc64/power7/memmove.S index 6988eff18f..e9a9cae6a4 100644 --- a/sysdeps/powerpc/powerpc64/power7/memmove.S +++ b/sysdeps/powerpc/powerpc64/power7/memmove.S @@ -425,7 +425,7 @@ L(end_unaligned_loop): /* Return original DST pointer. */ blr - /* Start to memcpy backward implementation: the algorith first check if + /* Start to memcpy backward implementation: the algorithm first check if src and dest have the same alignment and if it does align both to 16 bytes and copy using VSX instructions. If does not, align dest to 16 bytes and use VMX (altivec) instruction diff --git a/sysdeps/powerpc/powerpc64/power7/strcmp.S b/sysdeps/powerpc/powerpc64/power7/strcmp.S index c1c2a6f6b3..bd41639c5d 100644 --- a/sysdeps/powerpc/powerpc64/power7/strcmp.S +++ b/sysdeps/powerpc/powerpc64/power7/strcmp.S @@ -17,7 +17,7 @@ . */ /* The optimization is achieved here through cmpb instruction. - 8byte aligned strings are processed with double word comparision + 8byte aligned strings are processed with double word comparison and unaligned strings are handled effectively with loop unrolling technique */ diff --git a/sysdeps/powerpc/powerpc64/power7/strncpy.S b/sysdeps/powerpc/powerpc64/power7/strncpy.S index eec0c41ccb..8d55a0cbcc 100644 --- a/sysdeps/powerpc/powerpc64/power7/strncpy.S +++ b/sysdeps/powerpc/powerpc64/power7/strncpy.S @@ -479,7 +479,7 @@ L(storebyte2): rldicl r6, r3, 0, 61 /* Recalculate padding */ mr r7, r6 - /* src is algined */ + /* src is aligned */ L(srcaligndstunalign): mr r9, r3 mr r6, r7 diff --git a/sysdeps/powerpc/powerpc64/power7/strrchr.S b/sysdeps/powerpc/powerpc64/power7/strrchr.S index 7f730c8d5e..accff65f04 100644 --- a/sysdeps/powerpc/powerpc64/power7/strrchr.S +++ b/sysdeps/powerpc/powerpc64/power7/strrchr.S @@ -31,7 +31,7 @@ ENTRY_TOCLESS (STRRCHR) clrrdi r8,r3,3 /* Align the address to doubleword boundary. */ cmpdi cr7,r4,0 ld r12,0(r8) /* Load doubleword from memory. */ - li r9,0 /* used to store last occurence */ + li r9,0 /* used to store last occurrence */ li r0,0 /* Doubleword with null chars to use with cmpb. */ diff --git a/sysdeps/powerpc/powerpc64/power8/strcasestr.S b/sysdeps/powerpc/powerpc64/power8/strcasestr.S index 1d1eeceef7..2e88481abd 100644 --- a/sysdeps/powerpc/powerpc64/power8/strcasestr.S +++ b/sysdeps/powerpc/powerpc64/power8/strcasestr.S @@ -137,7 +137,7 @@ ENTRY (STRCASESTR, 4) beq cr7, L(skipcheck) cmpw cr7, r3, r29 ble cr7, L(firstpos) - /* Move r3 to the first occurence. */ + /* Move r3 to the first occurrence. */ L(skipcheck): mr r3, r29 L(firstpos): @@ -448,7 +448,7 @@ L(loop1): beq cr7, L(skipcheck1) cmpw cr7, r3, r29 ble cr7, L(nextpos) - /* Move r3 to first occurence. */ + /* Move r3 to first occurrence. */ L(skipcheck1): mr r3, r29 L(nextpos): diff --git a/sysdeps/powerpc/powerpc64/power8/strcmp.S b/sysdeps/powerpc/powerpc64/power8/strcmp.S index 4b1cde92ae..4b36723c84 100644 --- a/sysdeps/powerpc/powerpc64/power8/strcmp.S +++ b/sysdeps/powerpc/powerpc64/power8/strcmp.S @@ -207,7 +207,7 @@ L(check_source2_byte_loop): bdnz L(check_source2_byte_loop) /* If source2 is unaligned to doubleword, the code needs to check - on each interation if the unaligned doubleword access will cross + on each iteration if the unaligned doubleword access will cross a 4k page boundary. */ .align 5 L(loop_unaligned): diff --git a/sysdeps/powerpc/powerpc64/power8/strlen.S b/sysdeps/powerpc/powerpc64/power8/strlen.S index 4e1d884cc0..33a3e6af27 100644 --- a/sysdeps/powerpc/powerpc64/power8/strlen.S +++ b/sysdeps/powerpc/powerpc64/power8/strlen.S @@ -65,7 +65,7 @@ ENTRY_TOCLESS (STRLEN, 4) L(align64): /* Proceed to the old (POWER7) implementation, checking two doublewords - per iteraction. For the first 56 bytes, we will just check for null + per iteration. For the first 56 bytes, we will just check for null characters. After that, we will also check if we are 64-byte aligned so we can jump to the vectorized implementation. We will unroll these loops to avoid excessive branching. */ diff --git a/sysdeps/powerpc/powerpc64/power8/strncmp.S b/sysdeps/powerpc/powerpc64/power8/strncmp.S index b30f970c66..65d0db49f4 100644 --- a/sysdeps/powerpc/powerpc64/power8/strncmp.S +++ b/sysdeps/powerpc/powerpc64/power8/strncmp.S @@ -101,7 +101,7 @@ L(align_8b): b L(loop_ne_align_1) /* If source2 is unaligned to doubleword, the code needs to check - on each interation if the unaligned doubleword access will cross + on each iteration if the unaligned doubleword access will cross a 4k page boundary. */ .align 4 L(loop_ne_align_0): diff --git a/sysdeps/powerpc/powerpc64/power8/strncpy.S b/sysdeps/powerpc/powerpc64/power8/strncpy.S index 79a3d5aac3..9cfa08ef95 100644 --- a/sysdeps/powerpc/powerpc64/power8/strncpy.S +++ b/sysdeps/powerpc/powerpc64/power8/strncpy.S @@ -144,7 +144,7 @@ L(short_path_2): .align 4 L(short_path_loop): /* At this point, the induction variable, r5, as well as the pointers - to dest and src (r9 and r4, respectivelly) have been updated. + to dest and src (r9 and r4, respectively) have been updated. Note: The registers r7 and r10 are induction variables derived from r5. They are used to determine if the total number of writes has @@ -351,7 +351,7 @@ L(pagecross): cmpdi cr7,r9,0 bne cr7,L(short_path_prepare_2) - /* No null byte found in the 32 bytes readed and length not reached, + /* No null byte found in the 32 bytes read and length not reached, read source again using unaligned loads and store them. */ ld r9,0(r4) addi r29,r3,16 diff --git a/sysdeps/powerpc/powerpc64/power8/strnlen.S b/sysdeps/powerpc/powerpc64/power8/strnlen.S index a8495afad5..5bc62d6fbb 100644 --- a/sysdeps/powerpc/powerpc64/power8/strnlen.S +++ b/sysdeps/powerpc/powerpc64/power8/strnlen.S @@ -166,7 +166,7 @@ L(loop_64B): vminub v6,v3,v4 vminub v7,v5,v6 vcmpequb. v7,v7,v0 /* Check for null bytes. */ - addi r5,r5,64 /* Add pointer to next iteraction. */ + addi r5,r5,64 /* Add pointer to next iteration. */ bne cr6,L(found_64B) /* If found null bytes. */ bdnz L(loop_64B) /* Continue the loop if count > 0. */ diff --git a/sysdeps/powerpc/powerpc64/power8/strrchr.S b/sysdeps/powerpc/powerpc64/power8/strrchr.S index 62b4d493e7..dad2eb11b8 100644 --- a/sysdeps/powerpc/powerpc64/power8/strrchr.S +++ b/sysdeps/powerpc/powerpc64/power8/strrchr.S @@ -74,7 +74,7 @@ ENTRY_TOCLESS (STRRCHR) clrrdi r8,r3,3 /* Align the address to doubleword boundary. */ cmpdi cr7,r4,0 ld r12,0(r8) /* Load doubleword from memory. */ - li r9,0 /* Used to store last occurence. */ + li r9,0 /* Used to store last occurrence. */ li r0,0 /* Doubleword with null chars to use with cmpb. */ diff --git a/sysdeps/powerpc/powerpc64/setjmp-bug21895.c b/sysdeps/powerpc/powerpc64/setjmp-bug21895.c index 31eab6c422..d15541c9dd 100644 --- a/sysdeps/powerpc/powerpc64/setjmp-bug21895.c +++ b/sysdeps/powerpc/powerpc64/setjmp-bug21895.c @@ -20,7 +20,7 @@ #include #include -/* Copy r1 adress to a local variable. */ +/* Copy r1 address to a local variable. */ #define GET_STACK_POINTER(sp) \ ({ \ asm volatile ("mr %0, 1\n\t" \ -- cgit 1.4.1