mirror/glibc - mirror of git://sourceware.org/git/glibc.git

	Commit message (Collapse)	Author	Age	Files	Lines
*	Simplify AVX check	H.J. Lu	2011-09-07	1	-4/+1
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*	Move Atom-optimized code out of the way and together	Ulrich Drepper	2011-09-06	4	-4/+6
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*	Remove now-wrong comment	Ulrich Drepper	2011-09-06	1	-5/+0
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*	Fix whitespaces	Ulrich Drepper	2011-09-05	2	-2/+0
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*	Add Atom-optimized strchr and strrchr for x86-64	Liubov Dmitrieva	2011-09-05	5	-3/+851
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*	Add optimized x86-64 wcscmp	Ulrich Drepper	2011-09-05	1	-0/+936
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*	Fix minor CFI problem in regular x86-64 trampoline	Ulrich Drepper	2011-08-20	1	-1/+2
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*	Fix CFI info in x86-64 trampolines for non-AVX code	Ulrich Drepper	2011-08-20	2	-11/+19
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*	Minor optimization of popcount in l10nflist	Ulrich Drepper	2011-08-11	1	-0/+13
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*	Fix inline strncat/strncmp on x86	Andreas Schwab	2011-08-04	1	-1/+1
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*	One more typo in AVX test	Ulrich Drepper	2011-07-23	1	-2/+2
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*	Merge branch 'master' of ssh://sourceware.org/git/glibc	Ulrich Drepper	2011-07-23	2	-29/+27
\|\ \| \| \| \| \| \| \| \|	Conflicts: ChangeLog
\| *	Fix overflow bug is optimized strncat for x86-64	Ulrich Drepper	2011-07-21	2	-29/+27
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* \|	One more change to XSAVE patch	Ulrich Drepper	2011-07-22	1	-2/+4
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* \|	Fix AVX check	Andreas Schwab	2011-07-22	1	-6/+15
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*	Fix check for AVX enablement	Ulrich Drepper	2011-07-20	1	-5/+12
\| \| \| \| \|	The AVX bit is set if the CPU supports AVX. But this doesn't mean the kernel does. Add checks according to Intel's documentation.
*	Force :a_x86_64_ymm to be 16-byte aligned	Ulrich Drepper	2011-07-20	1	-3/+4
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*	Fix whitespaces	Ulrich Drepper	2011-07-19	4	-12/+9
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*	Improve 64 bit strcat functions with SSE2/SSSE3	Liubov Dmitrieva	2011-07-19	15	-318/+1486
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*	Rebuild configure scripts	Ulrich Drepper	2011-07-06	1	-1/+1
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*	Improved st{r,p}{,n}cpy for SSE2 and SSSE3 on x86-64	H.J. Lu	2011-06-24	10	-1838/+5488
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*	Optimized st{r,p}{,n}cpy for SSE2/SSSE3 on x86-32	H.J. Lu	2011-06-24	2	-3/+14
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*	Add an elf_ifunc_invoke interface so that architectures can implement	David S. Miller	2011-06-20	1	-1/+8
\| \| \| \|	the ifunc resolver calls however they wish.
*	Assume Intel Core i3/i5/i7 processor if AVX is available	H.J. Lu	2011-06-03	1	-0/+7
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*	Fix typo in x86-64 powl	H.J. Lu	2011-05-18	1	-2/+2
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*	Fix static linking with checking x86/x86-64 memcpy.	Mike Frysinger	2011-04-17	2	-2/+2
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*	Fix memory leak in TLS of loaded objects.	Ulrich Drepper	2011-04-10	1	-1/+4
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*	Fix typo in cache information table for x86-{32,64}.	Ulrich Drepper	2011-04-03	1	-1/+1
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*	Work around old buggy program which cannot cope with memcpy semantics.	H.J. Lu	2011-04-01	5	-5/+58
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*	Last change caused infinite loops because of missing loop increment.	Ulrich Drepper	2011-03-22	1	-0/+2
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*	Handle page boundaries in x86 SSE4.2 strncmp.	H.J. Lu	2011-03-21	1	-15/+30
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*	Implement x86 cpuid handling of leaf4 for cache information.	Ulrich Drepper	2011-03-20	1	-0/+49
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*	Enable SSE2 memset for AMD'supcoming Orochi processor.	Harsha Jagasia	2011-03-04	3	-50/+79
\| \| \| \| \| \| \| \| \|	This patch enables SSE2 memset for AMD's upcoming Orochi processor. This patch also fixes the following bug: For misaligned blocks larger than > 144 Bytes, memset branches into the integer code path depending on the value of misalignment even if the startup code chooses the SSE2 code path upfront, when multiarch is enabled.
*	Work around empty line at end file generated by autoconf.	Ulrich Drepper	2011-02-17	2	-0/+2
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*	Remove use of ranlib.	Ulrich Drepper	2011-02-15	1	-12/+91
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*	Fix some warning nits.	Roland McGrath	2011-02-04	1	-0/+1
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*	Clean up some bits/select.h headers.	Ulrich Drepper	2011-01-09	1	-3/+5
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*	Make PowerPC64 default to nonexecutable stack	Ryan S. Arnold	2010-12-19	1	-1/+7
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*	Support Intel processor model 6 and model 0x2.	H.J. Lu	2010-11-12	1	-0/+1
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*	Fix one exit path in x86-64 SSE4.2 str{,n}casecmp.	H.J. Lu	2010-11-10	1	-0/+6
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*	Fix warnings in __bswap_16.	Ulrich Drepper	2010-11-10	1	-14/+15
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*	Use IFUNC on x86-64 memset	H.J. Lu	2010-11-08	9	-156/+369
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*	32bit memset-sse2.S fails with uneven cache size	Ulrich Drepper	2010-11-05	1	-2/+18
\| \| \| \| \| \| \| \| \|	32bit memset-sse2.S assumes cache size is multiple of 128 bytes. If it isn't true, memset-sse2.S will fail. For example, a processor can have 24576 KB L3 cache and 20 cores. That is 2516582 byte per core. Half of it is 1258291, which isn't helpful for vector instructions. This patch rounds cache sizes to multiple of 256 bytes and adds "raw" cache sizes.
*	Fix x86-64 strchr propagation of search byte into all bytes of SSE register	Richard Li	2010-10-25	1	-2/+2
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*	Provide FP_FAST_FMA{,F,L} definitions for x86/x86-64.	Ulrich Drepper	2010-10-19	1	-1/+15
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*	Implement accurate fma.	Jakub Jelinek	2010-10-13	1	-2/+2
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*	Correct implementation of fmaf.	Jakub Jelinek	2010-10-11	3	-4/+6
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*	Fix handling of tail bytes of buffer in SSE2/SSSE3 x86-64 version strn{,case}cmp	Ulrich Drepper	2010-10-03	1	-16/+16
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*	Re-enable all strncasecmp versions.	Ulrich Drepper	2010-09-20	1	-2/+0
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*	Fix limit detection in x86-64 SSE2 strncasecmp.	Ulrich Drepper	2010-09-20	2	-1/+3
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