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* Change __x86_64 prefix in cache size to __x86H.J. Lu2013-01-051-27/+27
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* Update copyright notices with scripts/update-copyrights.Joseph Myers2013-01-021-1/+1
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* Replace FSF snail mail address with URLs.Paul Eggert2012-02-091-4/+2
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* Fix typo in cache information table for x86-{32,64}.Ulrich Drepper2011-04-031-1/+1
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* Last change caused infinite loops because of missing loop increment.Ulrich Drepper2011-03-221-0/+2
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* Implement x86 cpuid handling of leaf4 for cache information.Ulrich Drepper2011-03-201-0/+49
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* Enable SSE2 memset for AMD'supcoming Orochi processor.Harsha Jagasia2011-03-041-15/+34
| | | | | | | | | This patch enables SSE2 memset for AMD's upcoming Orochi processor. This patch also fixes the following bug: For misaligned blocks larger than > 144 Bytes, memset branches into the integer code path depending on the value of misalignment even if the startup code chooses the SSE2 code path upfront, when multiarch is enabled.
* 32bit memset-sse2.S fails with uneven cache sizeUlrich Drepper2010-11-051-2/+18
| | | | | | | | | 32bit memset-sse2.S assumes cache size is multiple of 128 bytes. If it isn't true, memset-sse2.S will fail. For example, a processor can have 24576 KB L3 cache and 20 cores. That is 2516582 byte per core. Half of it is 1258291, which isn't helpful for vector instructions. This patch rounds cache sizes to multiple of 256 bytes and adds "raw" cache sizes.
* Optimize 32bit memset/memcpy with SSE2/SSSE3.H.J. Lu2010-01-121-2/+8
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* Fix whitespaces in last checkin.Ulrich Drepper2009-08-071-1/+1
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* Properly count number of logical processors on Intel CPUs.H.J. Lu2009-08-071-4/+38
| | | | | | | | | | | | | | | | | | | | The meaning of the 25-14 bits in EAX returned from cpuid with EAX = 4 has been changed from "the maximum number of threads sharing the cache" to "the maximum number of addressable IDs for logical processors sharing the cache" if cpuid takes EAX = 11. We need to use results from both EAX = 4 and EAX = 11 to get the number of threads sharing the cache. The 25-14 bits in EAX on Core i7 is 15 although the number of logical processors is 8. Here is a white paper on this: http://software.intel.com/en-us/articles/intel-64-architecture-processor-topology-enumeration/ This patch correctly counts number of logical processors on Intel CPUs with EAX = 11 support on cpuid. Tested on Dinnington, Core i7 and Nehalem EX/EP. It also fixed Pentium Ds workaround since EBX may not have the right value returned from cpuid with EAX = 1.
* Support multiarch for i686.H.J. Lu2009-07-311-38/+41
| | | | | | This patch adds multiarch support when configured for i686. I modified some x86-64 functions to support 32bit. I will contribute 32bit SSE string and memory functions later.
* Avoid cpuid instructions in cache info discovery.Ulrich Drepper2009-07-231-19/+31
| | | | When multiarch is enabled we have this information stored. Use it.
* Add more cache descriptors for L3 caches on x86 and x86-64.Ulrich Drepper2009-07-231-0/+3
| | | | | The most recent AP 485 describes a few more cache descriptors for L3 caches with 24-way associativity.
* Simplify CPUID value handling.Ulrich Drepper2009-05-311-4/+4
| | | | | | | SO far Intel and AMD use exactly the same bits meaning the same things in CPUID index 1. Simplify the code. Should an architecture come along which doesn't use the same semantics then it must use a different index value than COMMON_CPUID_INDEX_1.
* Compact cache info data structure for x86/x86-64.Ulrich Drepper2009-05-291-77/+77
| | | | This saves about 1.5kB in the DSO.
* * version.h (VERSION): Bump to 2.10.1. cvs/fedora-glibc-20090510T1842 cvs/masterUlrich Drepper2009-05-101-0/+1
| | | | | | | | | | | | | | * nss/getXXbyYY_r.c: If NO_COMPAT_NEEDED is defined don't define any compatibility functions. * nss/getXXent_r.c: Likewise. * gshadow/getsgent_r.c: Define NO_COMPAT_NEEDED. * gshadow/getsgnam_r.c: Likewise. * gshadow/Version: Remove duplicate entries. * sysdeps/x86_64/cacheinfo.c (intel_02_cache_info): Add missing entries for recent processor. * sysdeps/unix/sysv/linux/i386/sysconf.c (intel_02_cache_info): Likewise.
* * config.h.in (USE_MULTIARCH): Define.Ulrich Drepper2009-03-131-4/+28
| | | | | | | | | | | | | | | | | | | | | | | | * configure.in: Handle --enable-multi-arch. * elf/dl-runtime.c (_dl_fixup): Handle STT_GNU_IFUNC. (_dl_fixup_profile): Likewise. * elf/do-lookup.c (dl_lookup_x): Likewise. * sysdeps/x86_64/dl-machine.h: Handle STT_GNU_IFUNC. * elf/elf.h (STT_GNU_IFUNC): Define. * include/libc-symbols.h (libc_ifunc): Define. * sysdeps/x86_64/cacheinfo.c: If USE_MULTIARCH is defined, use the framework in init-arch.h to get CPUID values. * sysdeps/x86_64/multiarch/Makefile: New file. * sysdeps/x86_64/multiarch/init-arch.c: New file. * sysdeps/x86_64/multiarch/init-arch.h: New file. * sysdeps/x86_64/multiarch/sched_cpucount.c: New file. * config.make.in (experimental-malloc): Define. * configure.in: Handle --enable-experimental-malloc. * malloc/Makefile: Handle experimental-malloc flag. * malloc/malloc.c: Implement PER_THREAD and ATOMIC_FASTBINS features. * malloc/arena.c: Likewise. * malloc/hooks.c: Likewise. * malloc/malloc.h: Define M_ARENA_TEST and M_ARENA_MAX.
* * sysdeps/x86_64/cacheinfo.c (intel_02_known): Add new descriptors.Ulrich Drepper2009-02-011-0/+14
| | | | * sysdeps/unix/sysv/linux/i386/sysconf.c (intel_02_known): Likewise.
* * sysdeps/x86_64/rtld-memset.c: New file.Ulrich Drepper2008-03-071-9/+1
| | | | | | | | | | | | | | | | | | | | | 2008-2-26 Harsha Jagasia <harsha.jagasia@amd.com> * sysdeps/x86_64/cacheinfo.c (NOT_USED_RIGHT_NOW): Remove ifdef guards. * sysdeps/x86_64/memset.S: Rewrite non-SSE code path as tuned for AMD Barcelona machine. Make default fall through branch of __x86_64_preferred_memory_instruction check as the integer code path. 2007-10-15 H.J. Lu <hongjiu.lu@intel.com> * sysdeps/x86_64/cacheinfo.c (__x86_64_preferred_memory_instruction): New variable. (init_cacheinfo): Initialize __x86_64_preferred_memory_instruction. * sysdeps/x86_64/memset.S: Rewrite. 2008-01-08 Jakub Jelinek <jakub@redhat.com> * malloc/malloc.c (public_cALLOc): For arenas other than
* (intel_02_known): New entry 0x3f.Ulrich Drepper2007-12-231-0/+1
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* * sysdeps/x86_64/cacheinfo.c: Comment out code added in support ofUlrich Drepper2007-10-171-0/+8
| | | | | | new memset. too high for the improvements. Implement bzero unconditionally for use in libc.
* * sysdeps/x86_64/cacheinfo.c (__x86_64_shared_cache_size): Define.Ulrich Drepper2007-10-161-4/+26
| | | | | | | | | | | | | | | | | | (init_cacheinfo): Initialize it. * sysdeps/x86_64/memset.S: Use __x86_64_shared_cache_size. Always define bzero. Remove non-glibc code. * sysdeps/x86_64/bzero.S: Make an empty file. 2007-10-15 H.J. Lu <hongjiu.lu@intel.com> * sysdeps/x86_64/cacheinfo.c (__x86_64_preferred_memory_instruction): New. (init_cacheinfo): Initialize __x86_64_preferred_memory_instruction. * sysdeps/x86_64/memset.S: Rewrite. * nss/getXXbyYY_r.c (REENTRANT_NAME): Mangle startp and start_fct
* * sysdeps/x86_64/cacheinfo.c (init_cacheinfo): Work around problemUlrich Drepper2007-10-101-0/+8
| | | | with some Pentium Ds.
* * sysdeps/x86_64/cacheinfo.c (__x86_64_data_cache_size_half): RenamedUlrich Drepper2007-09-221-18/+58
| | | | | | | | | from __x86_64_core_cache_size_half. (init_cacheinfo): Compute shared cache size for AMD processors with shared L3 correctly. * sysdeps/x86_64/memcpy.S: Adjust for __x86_64_data_cache_size_half name change. Patch in large parts by Evandro Menezes.
* * sysdeps/x86_64/cacheinfo.c (handle_amd): Fix computation of cvs/fedora-glibc-20070825T1839Ulrich Drepper2007-08-251-8/+6
| | | | associativity for fully-associative caches.
* * sysdeps/x86_64/cacheinfo.c (handle_amd): Handle L3 cacheUlrich Drepper2007-08-251-2/+56
| | | | | requests. Fill on more associativity values for L2. Patch mostly by Evandro Menezes.
* * sysdeps/x86_64/cacheinfo.c (intel_02_known): Add new entries.Ulrich Drepper2007-07-091-0/+2
| | | | * sysdeps/unix/sysv/linux/i386/sysconf.c (intel_02_known): Likewise.
* * sysdeps/x86_64/cacheinfo.c (init_cacheinfo): Pass correct valueUlrich Drepper2007-05-211-18/+19
| | | | as second parameter to handle_intel.
* * sysdeps/unix/sysv/linux/x86_64/sysconf.c: Move cache informationUlrich Drepper2007-05-211-0/+450
handling to ... * sysdeps/x86_64/cacheinfo.c: ... here. New file. * sysdeps/x86_64/Makefile [subdir=string] (sysdep_routines): Add cacheinfo. * sysdeps/x86_64/memcpy.S: Complete rewrite. * sysdeps/x86_64/mempcpy.S: Adjust appropriately. Patch by Evandro Menezes <evandro.menezes@amd.com>. * sysdeps/unix/sysv/linux/i386/epoll_pwait.S: New file.
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