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* Move shared pthread definitions to common headersAdhemerval Zanella2017-05-092-271/+99
* x86: Set dl_platform and dl_hwcap from CPU features [BZ #21391]H.J. Lu2017-05-035-1/+223
* x86: Use AVX2 memcpy/memset on Skylake server [BZ #21396]H.J. Lu2017-04-182-1/+8
* x86: Set Prefer_No_VZEROUPPER if AVX512ER is availableH.J. Lu2017-04-182-2/+21
* Consolidate pthreadtype.h placementConsolidate pthreadtype.h placementAdhemerval Zanella2017-04-101-0/+0
* Add sysdeps/x86/dl-procinfo.cH.J. Lu2017-04-101-0/+52
* Check if SSE is available with HAS_CPU_FEATUREH.J. Lu2017-04-071-0/+4
* Use CPU_FEATURES_CPU_P to check if AVX is availableH.J. Lu2017-03-171-2/+1
* Remove C++ namespace handling from glibc headers.Joseph Myers2017-03-161-14/+0
* Fix test-math-vector-sincos.h aliasing.Joseph Myers2017-03-151-14/+14
* Use index_cpu_RTM and reg_RTM to clear the bit_cpu_RTM bitH.J. Lu2017-02-171-1/+1
* New pthread rwlock that is more scalable.Torvald Riegel2017-01-101-14/+14
* Update copyright dates with scripts/update-copyrights.Joseph Myers2017-01-0133-33/+33
* New condvar implementation that provides stronger ordering guarantees.Torvald Riegel2016-12-311-8/+21
* Disable TSX on some Haswell processors.Andrew Senkevich2016-12-191-6/+23
* Refactor long double information into bits/long-double.h.Joseph Myers2016-12-141-20/+0
* Use C11-like atomics instead of plain memory accesses in x86 lock elision.Torvald Riegel2016-12-051-11/+19
* Refactor FP_ILOGB* out of bits/mathdef.h.Joseph Myers2016-12-012-9/+24
* Refactor FP_FAST_* into bits/fp-fast.h.Joseph Myers2016-11-291-14/+0
* Refactor float_t, double_t information into bits/flt-eval-method.h.Joseph Myers2016-11-242-17/+33
* Fix x86_64 -mfpmath=387 float_t, double_t (bug 20787).Joseph Myers2016-11-234-2/+9
* nptl: Document the reason why __kind in pthread_mutex_t is part of the ABIFlorian Weimer2016-11-071-1/+1
* Define wordsize.h macros everywhereSteve Ellcey2016-11-041-0/+4
* Bug 20689: Fix FMA and AVX2 detection on IntelCarlos O'Donell2016-10-171-10/+14
* X86: Don't assert on older Intel CPUs [BZ #20647]H.J. Lu2016-10-121-1/+3
* Add iseqsig.Joseph Myers2016-10-061-0/+28
* Installed header hygiene (BZ#20366): Test of installed headers.Zack Weinberg2016-09-231-0/+6
* Add femode_t functions.Joseph Myers2016-09-071-0/+14
* X86-64: Add _dl_runtime_resolve_avx[512]_{opt|slow} [BZ #20508]H.J. Lu2016-09-062-0/+20
* X86: Change bit_YMM_state to (1 << 2)H.J. Lu2016-08-191-1/+1
* Fixed wrong vector sincos/sincosf ABI to have it compatible withAndrew Senkevich2016-07-011-0/+98
* Check Prefer_ERMS in memmove/memcpy/mempcpy/memsetH.J. Lu2016-06-301-0/+3
* Avoid array-bounds warning for strncat on i586 (bug 20260)Andreas Schwab2016-06-291-2/+1
* Check FMA after COMMON_CPUID_INDEX_80000001H.J. Lu2016-06-071-4/+9
* Count number of logical processors sharing L2 cacheH.J. Lu2016-05-271-34/+116
* Remove special L2 cache case for Knights LandingH.J. Lu2016-05-201-2/+0
* Correct Intel processor level type mask from CPUIDH.J. Lu2016-05-191-1/+1
* Check the HTT bit before counting logical threadsH.J. Lu2016-05-192-76/+85
* Support non-inclusive caches on Intel processorsH.J. Lu2016-05-131-1/+11
* Remove x86 ifunc-defines.sym and rtld-global-offsets.symH.J. Lu2016-05-114-10/+18
* Move sysdeps/x86_64/cacheinfo.c to sysdeps/x86H.J. Lu2016-05-081-0/+673
* Detect Intel Goldmont and Airmont processorsH.J. Lu2016-04-151-0/+8
* Remove Fast_Copy_Backward from Intel Core processorsH.J. Lu2016-04-011-5/+1
* Initial Enhanced REP MOVSB/STOSB (ERMS) supportH.J. Lu2016-03-281-0/+4
* [x86] Add a feature bit: Fast_Unaligned_CopyH.J. Lu2016-03-282-1/+16
* Set index_arch_AVX_Fast_Unaligned_Load only for Intel processorsH.J. Lu2016-03-222-74/+88
* Add _arch_/_cpu_ to index_*/bit_* in x86 cpu-features.hH.J. Lu2016-03-102-147/+155
* Define _HAVE_STRING_ARCH_mempcpy to 1 for x86H.J. Lu2016-03-081-0/+3
* Add _STRING_INLINE_unaligned and string_private.hH.J. Lu2016-02-182-2/+22
* Set index_Fast_Unaligned_Load for Excavator family CPUsAmit Pawar2016-01-141-0/+8
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