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path: root/sysdeps/x86/dl-cacheinfo.h
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* x86: Enable non-temporal memset for Hygon processorsFeifei Wang2024-08-261-1/+1
* x86: Add cache information support for Hygon processorsFeifei Wang2024-08-261-0/+60
* x86: Add `Avoid_STOSB` tunable to allow NT memset without ERMSNoah Goldstein2024-08-151-5/+29
* x86: Use `Avoid_Non_Temporal_Memset` to control non-temporal pathNoah Goldstein2024-08-151-8/+7
* x86: Disable non-temporal memset on Skylake ServerNoah Goldstein2024-07-161-7/+8
* x86: Set default non_temporal_threshold for Zhaoxin processorsMayShao-oc2024-06-301-2/+4
* x86: Fix value for `x86_memset_non_temporal_threshold` when it is undesirableNoah Goldstein2024-06-141-3/+3
* x86: Enable non-temporal memset tunable for AMDJoe Damato2024-06-101-4/+4
* x86: Add seperate non-temporal tunable for memsetNoah Goldstein2024-05-301-0/+16
* x86: Do not prefer ERMS for memset on Zen3+Adhemerval Zanella2024-02-131-0/+5
* x86: Fix Zen3/Zen4 ERMS selection (BZ 30994)Adhemerval Zanella2024-02-131-20/+18
* Update copyright dates with scripts/update-copyrightsPaul Eggert2024-01-011-1/+1
* x86: Check the lower byte of EAX of CPUID leaf 2 [BZ #30643]H.J. Lu2023-08-291-18/+13
* x86: Fix incorrect scope of setting `shared_per_thread` [BZ# 30745]Noah Goldstein2023-08-111-4/+3
* x86: Fix for cache computation on AMD legacy cpus.Sajan Karumanchi2023-08-061-27/+199
* [PATCH v1] x86: Use `3/4*sizeof(per-thread-L3)` as low bound for NT threshold.Noah Goldstein2023-07-181-3/+12
* x86: Fix slight bug in `shared_per_thread` cache size calculation.Noah Goldstein2023-07-181-2/+2
* Fix misspellings -- BZ 25337Paul Pluzhnikov2023-06-191-1/+1
* x86: Make the divisor in setting `non_temporal_threshold` cpu specificNoah Goldstein2023-06-121-13/+19
* x86: Increase `non_temporal_threshold` to roughly `sizeof_L3 / 4`Noah Goldstein2023-06-121-27/+43
* x86: Use 64MB as nt-store threshold if no cacheinfo [BZ #30429]Noah Goldstein2023-05-271-1/+9
* x86/dl-cacheinfo: remove unsused parameter from handle_amdAndreas Schwab2023-04-041-36/+30
* Remove --enable-tunables configure optionAdhemerval Zanella Netto2023-03-291-10/+0
* x86: Cache computation for AMD architecture.Sajan Karumanchi2023-01-181-159/+45
* Update copyright dates with scripts/update-copyrightsJoseph Myers2023-01-061-1/+1
* x86: Check minimum/maximum of non_temporal_threshold [BZ #29953]H.J. Lu2023-01-031-9/+16
* x86: Add bounds `x86_non_temporal_threshold`Noah Goldstein2022-06-151-1/+7
* x86: Fix misordered logic for setting `rep_movsb_stop_threshold`Noah Goldstein2022-06-141-12/+12
* Update copyright dates with scripts/update-copyrightsPaul Eggert2022-01-011-1/+1
* x86: Double size of ERMS rep_movsb_threshold in dl-cacheinfo.hNoah Goldstein2021-11-061-3/+5
* x86: Set rep_movsb_threshold to 2112 on processors with FSRMH.J. Lu2021-05-031-0/+4
* x86: Handle _SC_LEVEL1_ICACHE_LINESIZE [BZ #27444]H.J. Lu2021-03-151-0/+6
* x86: Use SIZE_MAX instead of (long int)-1 for tunable range valueSiddhesh Poyarekar2021-02-101-5/+5
* tunables: Simplify TUNABLE_SET interfaceSiddhesh Poyarekar2021-02-101-9/+6
* x86: Adding an upper bound for Enhanced REP MOVSB.Sajan Karumanchi2021-02-021-1/+14
* <sys/platform/x86.h>: Remove the C preprocessor magicH.J. Lu2021-01-211-2/+2
* x86: Move x86 processor cache info to cpu_featuresH.J. Lu2021-01-141-0/+460
* Update copyright dates with scripts/update-copyrightsPaul Eggert2021-01-021-1/+1
* x86: Initialize CPU info via IFUNC relocation [BZ 26203]H.J. Lu2020-10-161-0/+478
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