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* x86: Correct bit_cpu_CLFSH [BZ #26208]H.J. Lu2020-07-061-1/+1
* x86: Detect Intel Advanced Matrix ExtensionsH.J. Lu2020-06-261-0/+20
* x86: Update CPU feature detection [BZ #26149]H.J. Lu2020-06-221-261/+158
* x86: Update F16C detection [BZ #26133]H.J. Lu2020-06-181-3/+3
* x86: Correct bit_cpu_CLFLUSHOPT [BZ #26128]H.J. Lu2020-06-171-1/+1
* x86: Add CPU Vendor ID detection support for Zhaoxin processorsmayshao2020-04-301-0/+1
* Update copyright dates with scripts/update-copyrights.Joseph Myers2020-01-011-1/+1
* Prefer https to http for gnu.org and fsf.org URLsPaul Eggert2019-09-071-1/+1
* Update copyright dates with scripts/update-copyrights.Joseph Myers2019-01-011-1/+1
* x86: Extend CPUID support in struct cpu_featuresH.J. Lu2018-12-031-194/+869
* Invert sense of list of i686-class processors in sysdeps/x86/cpu-features.h.Joseph Myers2018-09-201-18/+7
* x86: Move STATE_SAVE_OFFSET/STATE_SAVE_MASK to sysdep.hH.J. Lu2018-08-061-14/+0
* Rename the glibc.tune namespace to glibc.cpuSiddhesh Poyarekar2018-08-021-1/+1
* x86: Populate COMMON_CPUID_INDEX_80000001 for Intel CPUs [BZ #23459]H.J. Lu2018-07-261-1/+1
* x86: Correct index_cpu_LZCNT [BZ # 23456]H.J. Lu2018-07-261-1/+1
* x86-64: Check Prefer_FSRM in ifunc-memmove.hH.J. Lu2018-05-211-0/+2
* Initial Fast Short REP MOVSB (FSRM) supportH.J. Lu2018-05-211-0/+3
* Update copyright dates with scripts/update-copyrights.Joseph Myers2018-01-011-1/+1
* x86-64: Use fxsave/xsave/xsavec in _dl_runtime_resolve [BZ #21265]H.J. Lu2017-10-201-7/+27
* x86: Add MathVec_Prefer_No_AVX512 to cpu-features [BZ #21967]H.J. Lu2017-09-121-0/+2
* x86: Remove assembly versions of index_cpu_*/index_arch_*H.J. Lu2017-08-251-42/+1
* x86: Add IBT/SHSTK bits to cpu-featuresH.J. Lu2017-08-141-0/+8
* x86: Remove assembly versions of HAS_CPU_FEATURE/HAS_ARCH_FEATUREH.J. Lu2017-08-041-57/+0
* x86: Rename glibc.tune.ifunc to glibc.tune.hwcapsH.J. Lu2017-06-211-3/+3
* tunables: Add IFUNC selection and cache sizesH.J. Lu2017-06-201-0/+8
* x86-64: Optimize memcmp/wmemcmp with AVX2 and MOVBEH.J. Lu2017-06-051-0/+1
* x86: Set dl_platform and dl_hwcap from CPU features [BZ #21391]H.J. Lu2017-05-031-0/+15
* x86: Use AVX2 memcpy/memset on Skylake server [BZ #21396]H.J. Lu2017-04-181-0/+3
* x86: Set Prefer_No_VZEROUPPER if AVX512ER is availableH.J. Lu2017-04-181-0/+15
* Check if SSE is available with HAS_CPU_FEATUREH.J. Lu2017-04-071-0/+4
* Update copyright dates with scripts/update-copyrights.Joseph Myers2017-01-011-1/+1
* X86-64: Add _dl_runtime_resolve_avx[512]_{opt|slow} [BZ #20508]H.J. Lu2016-09-061-0/+6
* X86: Change bit_YMM_state to (1 << 2)H.J. Lu2016-08-191-1/+1
* Check Prefer_ERMS in memmove/memcpy/mempcpy/memsetH.J. Lu2016-06-301-0/+3
* Check the HTT bit before counting logical threadsH.J. Lu2016-05-191-0/+3
* Remove x86 ifunc-defines.sym and rtld-global-offsets.symH.J. Lu2016-05-111-2/+1
* Initial Enhanced REP MOVSB/STOSB (ERMS) supportH.J. Lu2016-03-281-0/+4
* [x86] Add a feature bit: Fast_Unaligned_CopyH.J. Lu2016-03-281-0/+3
* Set index_arch_AVX_Fast_Unaligned_Load only for Intel processorsH.J. Lu2016-03-221-2/+8
* Add _arch_/_cpu_ to index_*/bit_* in x86 cpu-features.hH.J. Lu2016-03-101-109/+113
* Update copyright dates with scripts/update-copyrights.Joseph Myers2016-01-041-1/+1
* Added memset optimized with AVX512 for KNL hardware.Andrew Senkevich2015-12-191-0/+4
* Add Prefer_MAP_32BIT_EXEC to map executable pages with MAP_32BIT hjl/32bit/masterH.J. Lu2015-12-151-0/+3
* Detect and select i586/i686 implementation at run-time fedora/masterH.J. Lu2015-08-271-3/+17
* Also check __i586__/__i686__ for HAS_I586/HAS_I686H.J. Lu2015-08-191-8/+9
* Define HAS_CPUID/HAS_I586/HAS_I686 from -march=H.J. Lu2015-08-181-0/+27
* Add _dl_x86_cpu_features to rtld_globalH.J. Lu2015-08-131-0/+240