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path: root/sysdeps/x86/cpu-features.c
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* x86-64: Simplify minimum ISA check ifdef conditional with ifSunil K Pandey2024-04-131-11/+8
* x86-64: Don't use SSE resolvers for ISA level 3 or aboveH.J. Lu2024-04-131-6/+11
* x86-64: Allocate state buffer space for RDI, RSI and RBXH.J. Lu2024-04-011-4/+7
* x86-64: Update _dl_tlsdesc_dynamic to preserve AMX registersH.J. Lu2024-04-011-2/+53
* x86: Update _dl_tlsdesc_dynamic to preserve caller-saved registersH.J. Lu2024-04-011-2/+54
* x86-64: Check if mprotect works before rewriting PLTH.J. Lu2024-01-151-1/+7
* i386: Remove CET support bitsH.J. Lu2024-01-101-1/+3
* elf: Add ELF_DYNAMIC_AFTER_RELOC to rewrite PLTH.J. Lu2024-01-051-1/+20
* Update copyright dates with scripts/update-copyrightsPaul Eggert2024-01-011-1/+1
* x86/cet: Don't set CET active by defaultH.J. Lu2024-01-011-1/+1
* x86/cet: Enable shadow stack during startupH.J. Lu2024-01-011-51/+0
* x86/cet: Sync with Linux kernel 6.6 shadow stack interfaceH.J. Lu2024-01-011-5/+10
* x86: Add support for AVX10 preset and vec size in cpu-featuresNoah Goldstein2023-09-291-0/+25
* <sys/platform/x86.h>: Add APX supportH.J. Lu2023-07-271-0/+4
* Fix misspellings -- BZ 25337Paul Pluzhnikov2023-06-191-1/+1
* x86: Make the divisor in setting `non_temporal_threshold` cpu specificNoah Goldstein2023-06-121-9/+22
* x86: Refactor Intel `init_cpu_features`Noah Goldstein2023-06-121-81/+309
* Fix misspellings in sysdeps/ -- BZ 25337Paul Pluzhnikov2023-05-301-1/+1
* <sys/platform/x86.h>: Add PREFETCHI supportH.J. Lu2023-04-051-0/+1
* <sys/platform/x86.h>: Add AMX-COMPLEX supportH.J. Lu2023-04-051-0/+2
* <sys/platform/x86.h>: Add AVX-NE-CONVERT supportH.J. Lu2023-04-051-0/+2
* <sys/platform/x86.h>: Add AVX-VNNI-INT8 supportH.J. Lu2023-04-051-0/+2
* <sys/platform/x86.h>: Add AVX-IFMA supportH.J. Lu2023-04-051-0/+2
* <sys/platform/x86.h>: Add AMX-FP16 supportH.J. Lu2023-04-051-0/+2
* <sys/platform/x86.h>: Add CMPCCXADD supportH.J. Lu2023-04-051-0/+1
* <sys/platform/x86.h>: Add RAO-INT supportH.J. Lu2023-04-051-0/+1
* x86: Set FSGSBASE to active if enabled by kernelH.J. Lu2023-04-031-0/+3
* Remove --enable-tunables configure optionAdhemerval Zanella Netto2023-03-291-19/+5
* x86-64: Add glibc.cpu.prefer_map_32bit_exec [BZ #28656]H.J. Lu2023-02-221-0/+15
* Update copyright dates with scripts/update-copyrightsJoseph Myers2023-01-061-1/+1
* x86: Black list more Intel CPUs for TSX [BZ #27398]H.J. Lu2022-01-181-3/+31
* Update copyright dates with scripts/update-copyrightsPaul Eggert2022-01-011-1/+1
* x86: Don't set Prefer_No_AVX512 for processors with AVX512 and AVX-VNNIH.J. Lu2021-12-061-2/+5
* x86-64: Remove Prefer_AVX2_STRCMPH.J. Lu2021-11-011-8/+0
* x86-64: Add Avoid_Short_Distance_REP_MOVSBH.J. Lu2021-07-281-0/+5
* x86: Install <bits/platform/x86.h> [BZ #27958]H.J. Lu2021-07-231-94/+94
* x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033]H.J. Lu2021-07-011-1/+4
* x86: Copy IBT and SHSTK usable only if CET is enabledH.J. Lu2021-06-231-2/+5
* x86: Set Prefer_No_VZEROUPPER and add Prefer_AVX2_STRCMPH.J. Lu2021-03-291-2/+18
* x86: Properly disable XSAVE related features [BZ #27605]H.J. Lu2021-03-291-0/+55
* x86: Add PTWRITE feature detection [BZ #27346]H.J. Lu2021-02-071-0/+8
* sysconf: Add _SC_MINSIGSTKSZ/_SC_SIGSTKSZ [BZ #20305]H.J. Lu2021-02-011-0/+3
* x86: Properly set usable CET feature bits [BZ #26625]H.J. Lu2021-01-291-2/+9
* <sys/platform/x86.h>: Remove the C preprocessor magicH.J. Lu2021-01-211-34/+34
* x86: Move x86 processor cache info to cpu_featuresH.J. Lu2021-01-141-27/+8
* x86: Support GNU_PROPERTY_X86_ISA_1_V[234] marker [BZ #26717]H.J. Lu2021-01-071-0/+3
* Update copyright dates with scripts/update-copyrightsPaul Eggert2021-01-021-1/+1
* x86: Set RDRAND usable if CPU supports RDRANDH.J. Lu2020-12-041-0/+1
* x86: Initialize CPU info via IFUNC relocation [BZ 26203]H.J. Lu2020-10-161-1/+11
* <sys/platform/x86.h>: Add FSRCS/FSRS/FZLRM supportH.J. Lu2020-10-091-0/+3
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