mirror/glibc - mirror of git://sourceware.org/git/glibc.git

	Commit message (Collapse)	Author	Age	Files	Lines
*	Update copyright dates with scripts/update-copyrights.	Joseph Myers	2017-01-01	1	-1/+1
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*	X86: Don't assert on older Intel CPUs [BZ #20647]	H.J. Lu	2016-10-12	1	-1/+3
\| \| \| \| \| \| \| \| \| \|	Since the maximum CPUID level of older Intel CPUs is 1, change handle_intel to return -1, instead of assert, when the maximum CPUID level is less than 2. [BZ #20647] * sysdeps/x86/cacheinfo.c (handle_intel): Return -1 if the maximum CPUID level is less than 2.
*	Count number of logical processors sharing L2 cache	H.J. Lu	2016-05-27	1	-34/+116
\| \| \| \| \| \| \| \| \| \| \| \| \|	For Intel processors, when there are both L2 and L3 caches, SMT level type should be ued to count number of available logical processors sharing L2 cache. If there is only L2 cache, core level type should be used to count number of available logical processors sharing L2 cache. Number of available logical processors sharing L2 cache should be used for non-inclusive L2 and L3 caches. * sysdeps/x86/cacheinfo.c (init_cacheinfo): Count number of available logical processors with SMT level type sharing L2 cache for Intel processors.
*	Remove special L2 cache case for Knights Landing	H.J. Lu	2016-05-20	1	-2/+0
\| \| \| \| \| \| \| \| \| \| \| \| \| \|	L2 cache is shared by 2 cores on Knights Landing, which has 4 threads per core: https://en.wikipedia.org/wiki/Xeon_Phi#Knights_Landing So L2 cache is shared by 8 threads on Knights Landing as reported by CPUID. We should remove special L2 cache case for Knights Landing. [BZ #18185] * sysdeps/x86/cacheinfo.c (init_cacheinfo): Don't limit threads sharing L2 cache to 2 for Knights Landing.
*	Correct Intel processor level type mask from CPUID	H.J. Lu	2016-05-19	1	-1/+1
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Intel CPUID with EAX == 11 returns: ECX Bits 07 - 00: Level number. Same value in ECX input. Bits 15 - 08: Level type. ^^^^^^^^^^^^^^^^^^^^^^^^ This is level type. Bits 31 - 16: Reserved. Intel processor level type mask should be 0xff00, not 0xff0. [BZ #20119] * sysdeps/x86/cacheinfo.c (init_cacheinfo): Correct Intel processor level type mask for CPUID with EAX == 11.
*	Check the HTT bit before counting logical threads	H.J. Lu	2016-05-19	1	-76/+82
\| \| \| \| \| \| \| \| \| \| \|	Skip counting logical threads for Intel processors if the HTT bit is 0 which indicates there is only a single logical processor. * sysdeps/x86/cacheinfo.c (init_cacheinfo): Skip counting logical threads if the HTT bit is 0. * sysdeps/x86/cpu-features.h (bit_cpu_HTT): New. (index_cpu_HTT): Likewise. (reg_HTT): Likewise.
*	Support non-inclusive caches on Intel processors	H.J. Lu	2016-05-13	1	-1/+11
\| \| \| \| \|	* sysdeps/x86/cacheinfo.c (init_cacheinfo): Check and support non-inclusive caches on Intel processors.
*	Move sysdeps/x86_64/cacheinfo.c to sysdeps/x86	H.J. Lu	2016-05-08	1	-0/+673
	Move sysdeps/x86_64/cacheinfo.c to sysdeps/x86. No code changes on x86 and x86_64. * sysdeps/i386/cacheinfo.c: Include <sysdeps/x86/cacheinfo.c> instead of <sysdeps/x86_64/cacheinfo.c>. * sysdeps/x86_64/cacheinfo.c: Moved to ... * sysdeps/x86/cacheinfo.c: Here.