| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Count number of logical processors sharing L2 cache hjl/erms/2.23 | H.J. Lu | 2016-06-06 | 1 | -34/+116 |
| * | Remove special L2 cache case for Knights Landing | H.J. Lu | 2016-06-06 | 1 | -2/+0 |
| * | Correct Intel processor level type mask from CPUID | H.J. Lu | 2016-06-06 | 1 | -1/+1 |
| * | Check the HTT bit before counting logical threads | H.J. Lu | 2016-06-06 | 1 | -76/+82 |
| * | Support non-inclusive caches on Intel processors | H.J. Lu | 2016-06-06 | 1 | -1/+11 |
| * | Move sysdeps/x86_64/cacheinfo.c to sysdeps/x86 | H.J. Lu | 2016-06-06 | 1 | -0/+673 |
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index : mirror/glibc | |
| mirror of git://sourceware.org/git/glibc.git | Leah Neukirchen |
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