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* Update copyright dates with scripts/update-copyrightsPaul Eggert2024-01-011-1/+1
* Update copyright dates with scripts/update-copyrightsJoseph Myers2023-01-061-1/+1
* Update copyright dates with scripts/update-copyrightsPaul Eggert2022-01-011-1/+1
* x86: Handle _SC_LEVEL1_ICACHE_LINESIZE [BZ #27444]H.J. Lu2021-03-151-0/+3
* Fix misplaced constAndreas Schwab2021-01-251-1/+1
* x86: Move x86 processor cache info to cpu_featuresH.J. Lu2021-01-141-12/+34
* Update copyright dates with scripts/update-copyrightsPaul Eggert2021-01-021-1/+1
* x86: Initialize CPU info via IFUNC relocation [BZ 26203]H.J. Lu2020-10-161-854/+14
* Reversing calculation of __x86_shared_non_temporal_thresholdPatrick McGehearty2020-09-281-5/+11
* x86: Support usable check for all CPU featuresH.J. Lu2020-07-131-6/+6
* x86: Remove the unused __x86_prefetchwH.J. Lu2020-07-111-16/+0
* x86: Add thresholds for "rep movsb/stosb" to tunablesH.J. Lu2020-07-061-0/+36
* i386: Remove unused variable in sysdeps/x86/cacheinfo.cFlorian Weimer2020-04-301-1/+1
* x86: Add cache information support for Zhaoxin processorsmayshao-oc2020-04-301-196/+282
* Update copyright dates with scripts/update-copyrights.Joseph Myers2020-01-011-1/+1
* Prefer https to http for gnu.org and fsf.org URLsPaul Eggert2019-09-071-1/+1
* Update copyright dates with scripts/update-copyrights.Joseph Myers2019-01-011-1/+1
* x86: Extend CPUID support in struct cpu_featuresH.J. Lu2018-12-031-10/+10
* Update copyright dates with scripts/update-copyrights.Joseph Myers2018-01-011-1/+1
* tunables: Add IFUNC selection and cache sizesH.J. Lu2017-06-201-1/+9
* x86: Don't use dl_x86_cpu_features in cacheinfo.cH.J. Lu2017-06-051-15/+22
* x86: Update __x86_shared_non_temporal_thresholdH.J. Lu2017-06-021-2/+4
* x86: Don't include cacheinfo.c in ld.soH.J. Lu2017-05-241-0/+4
* x86: Use __get_cpu_features to get cpu_featuresH.J. Lu2017-05-241-10/+9
* Update copyright dates with scripts/update-copyrights.Joseph Myers2017-01-011-1/+1
* X86: Don't assert on older Intel CPUs [BZ #20647]H.J. Lu2016-10-121-1/+3
* Count number of logical processors sharing L2 cacheH.J. Lu2016-05-271-34/+116
* Remove special L2 cache case for Knights LandingH.J. Lu2016-05-201-2/+0
* Correct Intel processor level type mask from CPUIDH.J. Lu2016-05-191-1/+1
* Check the HTT bit before counting logical threadsH.J. Lu2016-05-191-76/+82
* Support non-inclusive caches on Intel processorsH.J. Lu2016-05-131-1/+11
* Move sysdeps/x86_64/cacheinfo.c to sysdeps/x86H.J. Lu2016-05-081-0/+673
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