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* powerpc: Installed-header hygieneTulio Magno Quites Machado Filho2016-10-041-9/+9
| | | | | | | | Fix powerpc-specific headers: - Make it compatible to C89 by replace references to inline by __inline__. - Get the definition of sigset_t used by sysdeps/unix/sysv/linux/powerpc/sys/ucontext.h. - Includes missing header file.
* powerpc: Fix POWER9 impliesTulio Magno Quites Machado Filho2016-09-192-2/+1
| | | | | Fix multiarch build for POWER9 by correcting the order of the directories listed at sysnames configure variable.
* Add e500 version of fetestexceptflag.Joseph Myers2016-09-071-0/+25
| | | | | | | | | | | | | | | When I added fetestexceptflag, I missed that e500 was another case that needed its own version because saved exceptions were not directly stored in a form that could be ANDed with exception bits (they were stored with exceptions in SPE form, but the FE_* macros always use the classic hard-float form). This patch adds an e500 version with the required call to __fexcepts_from_spe to convert from one form to the other. Tested for e500. * sysdeps/powerpc/powerpc32/e500/nofpu/fetestexceptflag.c: New file.
* Add femode_t functions: powerpc.Joseph Myers2016-09-076-0/+222
| | | | | | | | | | | This patch adds PowerPC versions of fegetmode and fesetmode. * sysdeps/powerpc/fpu/fegetmode.c: New file. * sysdeps/powerpc/fpu/fesetmode.c: Likewise. * sysdeps/powerpc/nofpu/fegetmode.c: Likewise. * sysdeps/powerpc/nofpu/fesetmode.c: Likewise. * sysdeps/powerpc/powerpc32/e500/nofpu/fegetmode.c: Likewise. * sysdeps/powerpc/powerpc32/e500/nofpu/fesetmode.c: Likewise.
* Add femode_t functions.Joseph Myers2016-09-075-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TS 18661-1 defines a type femode_t to represent the set of dynamic floating-point control modes (such as the rounding mode and trap enablement modes), and functions fegetmode and fesetmode to manipulate those modes (without affecting other state such as the raised exception flags) and a corresponding macro FE_DFL_MODE. This patch series implements those interfaces for glibc. This first patch adds the architecture-independent pieces, the x86 and x86_64 implementations, and the <bits/fenv.h> and ABI baseline updates for all architectures so glibc keeps building and passing the ABI tests on all architectures. Subsequent patches add the fegetmode and fesetmode implementations for other architectures. femode_t is generally an integer type - the same type as fenv_t, or as the single element of fenv_t where fenv_t is a structure containing a single integer (or the single relevant element, where it has elements for both status and control registers) - except where architecture properties or consistency with the fenv_t implementation indicate otherwise. FE_DFL_MODE follows FE_DFL_ENV in whether it's a magic pointer value (-1 cast to const femode_t *), a value that can be distinguished from valid pointers by its high bits but otherwise contains a representation of the desired register contents, or a pointer to a constant variable (the powerpc case; __fe_dfl_mode is added as an exported constant object, an alias to __fe_dfl_env). Note that where architectures (that share a register between control and status bits) gain definitions of new floating-point control or status bits in future, the implementations of fesetmode for those architectures may need updating (depending on whether the new bits are control or status bits and what the implementation does with previously unknown bits), just like existing implementations of <fenv.h> functions that take care not to touch reserved bits may need updating when the set of reserved bits changes. (As any new bits are outside the scope of ISO C, that's just a quality-of-implementation issue for supporting them, not a conformance issue.) As with fenv_t, femode_t should properly include any software DFP rounding mode (and for both fenv_t and femode_t I'd consider that fragment of DFP support appropriate for inclusion in glibc even in the absence of the rest of libdfp; hardware DFP rounding modes should already be included if the definitions of which bits are status / control bits are correct). Tested for x86_64, x86, mips64 (hard float, and soft float to test the fallback version), arm (hard float) and powerpc (hard float, soft float and e500). Other architecture versions are untested. * math/fegetmode.c: New file. * math/fesetmode.c: Likewise. * sysdeps/i386/fpu/fegetmode.c: Likewise. * sysdeps/i386/fpu/fesetmode.c: Likewise. * sysdeps/x86_64/fpu/fegetmode.c: Likewise. * sysdeps/x86_64/fpu/fesetmode.c: Likewise. * math/fenv.h: Update comment on inclusion of <bits/fenv.h>. [__GLIBC_USE (IEC_60559_BFP_EXT)] (fegetmode): New function declaration. [__GLIBC_USE (IEC_60559_BFP_EXT)] (fesetmode): Likewise. * bits/fenv.h [__GLIBC_USE (IEC_60559_BFP_EXT)] (femode_t): New typedef. [__GLIBC_USE (IEC_60559_BFP_EXT)] (FE_DFL_MODE): New macro. * sysdeps/aarch64/bits/fenv.h [__GLIBC_USE (IEC_60559_BFP_EXT)] (femode_t): New typedef. [__GLIBC_USE (IEC_60559_BFP_EXT)] (FE_DFL_MODE): New macro. * sysdeps/alpha/fpu/bits/fenv.h [__GLIBC_USE (IEC_60559_BFP_EXT)] (femode_t): New typedef. [__GLIBC_USE (IEC_60559_BFP_EXT)] (FE_DFL_MODE): New macro. * sysdeps/arm/bits/fenv.h [__GLIBC_USE (IEC_60559_BFP_EXT)] (femode_t): New typedef. [__GLIBC_USE (IEC_60559_BFP_EXT)] (FE_DFL_MODE): New macro. * sysdeps/hppa/fpu/bits/fenv.h [__GLIBC_USE (IEC_60559_BFP_EXT)] (femode_t): New typedef. [__GLIBC_USE (IEC_60559_BFP_EXT)] (FE_DFL_MODE): New macro. * sysdeps/ia64/bits/fenv.h [__GLIBC_USE (IEC_60559_BFP_EXT)] (femode_t): New typedef. [__GLIBC_USE (IEC_60559_BFP_EXT)] (FE_DFL_MODE): New macro. * sysdeps/m68k/fpu/bits/fenv.h [__GLIBC_USE (IEC_60559_BFP_EXT)] (femode_t): New typedef. [__GLIBC_USE (IEC_60559_BFP_EXT)] (FE_DFL_MODE): New macro. * sysdeps/microblaze/bits/fenv.h [__GLIBC_USE (IEC_60559_BFP_EXT)] (femode_t): New typedef. [__GLIBC_USE (IEC_60559_BFP_EXT)] (FE_DFL_MODE): New macro. * sysdeps/mips/bits/fenv.h [__GLIBC_USE (IEC_60559_BFP_EXT)] (femode_t): New typedef. [__GLIBC_USE (IEC_60559_BFP_EXT)] (FE_DFL_MODE): New macro. * sysdeps/nios2/bits/fenv.h [__GLIBC_USE (IEC_60559_BFP_EXT)] (femode_t): New typedef. [__GLIBC_USE (IEC_60559_BFP_EXT)] (FE_DFL_MODE): New macro. * sysdeps/powerpc/bits/fenv.h [__GLIBC_USE (IEC_60559_BFP_EXT)] (femode_t): New typedef. [__GLIBC_USE (IEC_60559_BFP_EXT)] (__fe_dfl_mode): New variable declaration. [__GLIBC_USE (IEC_60559_BFP_EXT)] (FE_DFL_MODE): New macro. * sysdeps/s390/fpu/bits/fenv.h [__GLIBC_USE (IEC_60559_BFP_EXT)] (femode_t): New typedef. [__GLIBC_USE (IEC_60559_BFP_EXT)] (FE_DFL_MODE): New macro. * sysdeps/sh/bits/fenv.h [__GLIBC_USE (IEC_60559_BFP_EXT)] (femode_t): New typedef. [__GLIBC_USE (IEC_60559_BFP_EXT)] (FE_DFL_MODE): New macro. * sysdeps/sparc/fpu/bits/fenv.h [__GLIBC_USE (IEC_60559_BFP_EXT)] (femode_t): New typedef. [__GLIBC_USE (IEC_60559_BFP_EXT)] (FE_DFL_MODE): New macro. * sysdeps/tile/bits/fenv.h [__GLIBC_USE (IEC_60559_BFP_EXT)] (femode_t): New typedef. [__GLIBC_USE (IEC_60559_BFP_EXT)] (FE_DFL_MODE): New macro. * sysdeps/x86/fpu/bits/fenv.h [__GLIBC_USE (IEC_60559_BFP_EXT)] (femode_t): New typedef. [__GLIBC_USE (IEC_60559_BFP_EXT)] (FE_DFL_MODE): New macro. * manual/arith.texi (FE_DFL_MODE): Document macro. (fegetmode): Document function. (fesetmode): Likewise. * math/Versions (fegetmode): New libm symbol at version GLIBC_2.25. (fesetmode): Likewise. * math/Makefile (libm-support): Add fegetmode and fesetmode. (tests): Add test-femode and test-femode-traps. * math/test-femode-traps.c: New file. * math/test-femode.c: Likewise. * sysdeps/powerpc/fpu/fenv_const.c (__fe_dfl_mode): Declare as alias for __fe_dfl_env. * sysdeps/powerpc/nofpu/fenv_const.c (__fe_dfl_mode): Likewise. * sysdeps/powerpc/powerpc32/e500/nofpu/fenv_const.c (__fe_dfl_mode): Likewise. * sysdeps/powerpc/Versions (__fe_dfl_mode): New libm symbol at version GLIBC_2.25. * sysdeps/nacl/libm.abilist: Update. * sysdeps/unix/sysv/linux/aarch64/libm.abilist: Likewise. * sysdeps/unix/sysv/linux/alpha/libm.abilist: Likewise. * sysdeps/unix/sysv/linux/arm/libm.abilist: Likewise. * sysdeps/unix/sysv/linux/hppa/libm.abilist: Likewise. * sysdeps/unix/sysv/linux/i386/libm.abilist: Likewise. * sysdeps/unix/sysv/linux/ia64/libm.abilist: Likewise. * sysdeps/unix/sysv/linux/m68k/coldfire/libm.abilist: Likewise. * sysdeps/unix/sysv/linux/m68k/m680x0/libm.abilist: Likewise. * sysdeps/unix/sysv/linux/microblaze/libm.abilist: Likewise. * sysdeps/unix/sysv/linux/mips/mips32/libm.abilist: Likewise. * sysdeps/unix/sysv/linux/mips/mips64/libm.abilist: Likewise. * sysdeps/unix/sysv/linux/nios2/libm.abilist: Likewise. * sysdeps/unix/sysv/linux/powerpc/powerpc32/fpu/libm.abilist: Likewise. * sysdeps/unix/sysv/linux/powerpc/powerpc32/nofpu/libm.abilist: Likewise. * sysdeps/unix/sysv/linux/powerpc/powerpc64/libm-le.abilist: Likewise. * sysdeps/unix/sysv/linux/powerpc/powerpc64/libm.abilist: Likewise. * sysdeps/unix/sysv/linux/s390/s390-32/libm.abilist: Likewise. * sysdeps/unix/sysv/linux/s390/s390-64/libm.abilist: Likewise. * sysdeps/unix/sysv/linux/sh/libm.abilist: Likewise. * sysdeps/unix/sysv/linux/sparc/sparc32/libm.abilist: Likewise. * sysdeps/unix/sysv/linux/sparc/sparc64/libm.abilist: Likewise. * sysdeps/unix/sysv/linux/tile/tilegx/tilegx32/libm.abilist: Likewise. * sysdeps/unix/sysv/linux/tile/tilegx/tilegx64/libm.abilist: Likewise. * sysdeps/unix/sysv/linux/tile/tilepro/libm.abilist: Likewise. * sysdeps/unix/sysv/linux/x86_64/64/libm.abilist: Likewise. * sysdeps/unix/sysv/linux/x86_64/x32/libm.abilist: Likewise.
* Add fesetexcept: powerpc.Joseph Myers2016-08-163-0/+107
| | | | | | | | This patch adds PowerPC versions of fesetexcept. * sysdeps/powerpc/fpu/fesetexcept.c: New file. * sysdeps/powerpc/nofpu/fesetexcept.c: Likewise. * sysdeps/powerpc/powerpc32/e500/nofpu/fesetexcept.c: Likewise.
* Add comment from sysdeps/powerpc/fpu/fraiseexcpt.c to fsetexcptflg.c.Joseph Myers2016-08-121-0/+1
| | | | | * sysdeps/powerpc/fpu/fsetexcptflg.c (__fesetexceptflag): Add comment from fraiseexcpt.c.
* Fix powerpc fesetexceptflag clearing FE_INVALID (bug 20455).Joseph Myers2016-08-101-1/+4
| | | | | | | | | | | | | | | | As shown by the test math/test-fexcept, the powerpc fesetexceptflag implementation fails to clear a previously set FE_INVALID flag, when that flag is clear in the saved exceptions and FE_INVALID is included in the mask of flags to restore, because it fails to mask out the sub-exceptions of FE_INVALID from the FPSCR state. This patch fixes the masking logic accordingly. Tested for powerpc. [BZ #20455] * sysdeps/powerpc/fpu/fsetexcptflg.c (__fesetexceptflag): Mask out all FE_INVALID sub-exceptions from FPSCR when FE_INVALID specified to be restored.
* Add tests for fegetexceptflag, fesetexceptflag.Joseph Myers2016-08-101-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | I noticed that there was no meaningful test coverage for fegetexceptflag and fesetexceptflag (one test ensures that calls to them compile and link, but nothing to verify they work correctly). This patch adds tests for these functions. fesetexceptflag is meant to set the relevant exception flag bits to the saved state without causing enabled traps to be taken. On some architectures, it is not possible to set exception flag bits without causing enabled traps to occur. Such architectures need to define EXCEPTION_SET_FORCES_TRAP to 1 in their math-tests.h, as is done in this patch for powerpc. x86 avoids needing to define this because the traps resulting from setting exception bits don't occur until the next floating-point operation or fwait instruction. Tested for x86_64, x86 and powerpc. Note that test-fexcept fails for powerpc because of a pre-existing bug in fesetexceptflag for powerpc, which I'll fix separately. * math/test-fexcept-traps.c: New file. * math/test-fexcept.c: Likewise. * math/Makefile (tests): Add test-fexcept and test-fexcept-traps. * sysdeps/generic/math-tests.h (EXCEPTION_SET_FORCES_TRAP): New macro. * sysdeps/powerpc/math-tests.h [!__NO_FPRS__] (EXCEPTION_SET_FORCES_TRAP): Likewise.
* powerpc: fix ifunc-sel.h fix asm constraints and clobber listAurelien Jarno2016-08-031-2/+4
| | | | | | | | | | | | | | | As pointer out on the mailing list, the inline assembly code in sysdeps/powerpc/ifunc-sel.h doesn't have a list of clobbered registers and used wrong constraints. This patch fixes that. I verified it doesn't introduce any change in the generated code. Changelog: * sysdeps/powerpc/ifunc-sel.h (ifunc_sel): Add "11", "12", "cr0" to the clobber list. Use "i" constraint instead of "X". (ifunc_one): Add "12" to the clobber list. Use "i" constraint instead of "X".
* powerpc: fix ifunc-sel.h with GCC 6Aurelien Jarno2016-08-031-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On 32-bit PowerPC GCC 6 always saves the PIC register on the stack in the prologue and adjust the stack in the epilogue. It is therefore not possible anymore to just exit the function in the inline asm code, otherwise it corrupts the stack pointer. This causes the following tests to fail when using GCC 6: FAIL: elf/ifuncmain1 FAIL: elf/ifuncmain1pic FAIL: elf/ifuncmain1picstatic FAIL: elf/ifuncmain1pie FAIL: elf/ifuncmain1staticpic FAIL: elf/ifuncmain1staticpie FAIL: elf/ifuncmain1vis FAIL: elf/ifuncmain1vispic FAIL: elf/ifuncmain1vispie FAIL: elf/ifuncmain2pic FAIL: elf/ifuncmain2picstatic FAIL: elf/ifuncmain3 FAIL: elf/ifuncmain4picstatic FAIL: elf/ifuncmain5 FAIL: elf/ifuncmain5picstatic FAIL: elf/ifuncmain5staticpic The solution is to replace the beqlr instructions by a beq to the end of the inline asm code. This fixes all the above failures. ChangeLog: * sysdeps/powerpc/ifunc-sel.h (ifunc_sel): Replace beqlr instructions by beq instructions jumping to the end of the function.
* ppc: Fix modf (sNaN) for pre-POWER5+ CPU (bug 20240).Aurelien Jarno2016-07-082-0/+10
| | | | | | | | | | | | | | | | Commit a6a4395d fixed modf implementation by compiling s_modf.c and s_modff.c with -fsignaling-nans. However these files are also included from the pre-POWER5+ implementation, and thus these files should also be compiled with -fsignaling-nans. Changelog: [BZ #20240] * sysdeps/powerpc/powerpc32/power4/fpu/multiarch/Makefile (CFLAGS-s_modf-ppc32.c): New variable. (CFLAGS-s_modff-ppc32.c): Likewise. * sysdeps/powerpc/powerpc64/fpu/multiarch/Makefile (CFLAGS-s_modf-ppc64.c): Likewise. (CFLAGS-s_modff-ppc64.c): Likewise.
* powerpc: Fix return code of strcasecmp for unaligned inputsRajalakshmi Srinivasaraghavan2016-07-051-3/+14
| | | | | | | If the input values are unaligned and if there are null characters in the memory before the starting address of the input values, strcasecmp gives incorrect return code. Fixed it by adding mask the bits that are not part of the string.
* powerpc: Add a POWER8-optimized version of sinf()Anton Blanchard2016-06-305-1/+604
| | | | | This uses the implementation of sinf() in sysdeps/x86_64/fpu/s_sinf.S as inspiration.
* powerpc: Add a POWER8-optimized version of expf()Tulio Magno Quites Machado Filho2016-06-306-1/+388
| | | | | | | | This implementation is based on the one already used at sysdeps/x86_64/fpu/e_expf.S. This implementation improves the performance by ~14% on average in synthetic benchmarks at the cost of decreasing accuracy to 1 ULP.
* Remove atomic_compare_and_exchange_bool_rel.Torvald Riegel2016-06-243-58/+0
| | | | | | | | | | | | | | | | | | | | | | | | atomic_compare_and_exchange_bool_rel and catomic_compare_and_exchange_bool_rel are removed and replaced with the new C11-like atomic_compare_exchange_weak_release. The concurrent code in nscd/cache.c has not been reviewed yet, so this patch does not add detailed comments. * nscd/cache.c (cache_add): Use new C11-like atomic operation instead of atomic_compare_and_exchange_bool_rel. * nptl/pthread_mutex_unlock.c (__pthread_mutex_unlock_full): Likewise. * include/atomic.h (atomic_compare_and_exchange_bool_rel, catomic_compare_and_exchange_bool_rel): Remove. * sysdeps/aarch64/atomic-machine.h (atomic_compare_and_exchange_bool_rel): Likewise. * sysdeps/alpha/atomic-machine.h (atomic_compare_and_exchange_bool_rel): Likewise. * sysdeps/arm/atomic-machine.h (atomic_compare_and_exchange_bool_rel): Likewise. * sysdeps/mips/atomic-machine.h (atomic_compare_and_exchange_bool_rel): Likewise. * sysdeps/tile/atomic-machine.h (atomic_compare_and_exchange_bool_rel): Likewise.
* elf: Consolidate machine-agnostic DTV definitions in <dl-dtv.h>Florian Weimer2016-06-202-14/+1
| | | | | Identical definitions of dtv_t and TLS_DTV_UNALLOCATED were repeated for all architectures using DTVs.
* Use generic fdim on more architectures (bug 6796, bug 20255, bug 20256).Joseph Myers2016-06-144-66/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some architectures have their own versions of fdim functions, which are missing errno setting (bug 6796) and may also return sNaN instead of qNaN for sNaN input, in the case of the x86 / x86_64 long double versions (bug 20256). These versions are not actually doing anything that a compiler couldn't generate, just straightforward comparisons / arithmetic (and, in the x86 / x86_64 case, testing for NaNs with fxam, which isn't actually needed once you use an unordered comparison and let the NaNs pass through the same subtraction as non-NaN inputs). This patch removes the x86 / x86_64 / powerpc versions, so that those architectures use the generic C versions, which correctly handle setting errno and deal properly with sNaN inputs. This seems better than dealing with setting errno in lots of .S versions. The i386 versions also return results with excess range and precision, which is not appropriate for a function exactly defined by reference to IEEE operations. For errno setting to work correctly on overflow, it's necessary to remove excess range with math_narrow_eval, which this patch duly does in the float and double versions so that the tests can reliably pass on x86. For float, this avoids any double rounding issues as the long double precision is more than twice that of float. For double, double rounding issues will need to be addressed separately, so this patch does not fully fix bug 20255. Tested for x86_64, x86 and powerpc. [BZ #6796] [BZ #20255] [BZ #20256] * math/s_fdim.c: Include <math_private.h>. (__fdim): Use math_narrow_eval on result. * math/s_fdimf.c: Include <math_private.h>. (__fdimf): Use math_narrow_eval on result. * sysdeps/i386/fpu/s_fdim.S: Remove file. * sysdeps/i386/fpu/s_fdimf.S: Likewise. * sysdeps/i386/fpu/s_fdiml.S: Likewise. * sysdeps/i386/i686/fpu/s_fdim.S: Likewise. * sysdeps/i386/i686/fpu/s_fdimf.S: Likewise. * sysdeps/i386/i686/fpu/s_fdiml.S: Likewise. * sysdeps/powerpc/fpu/s_fdim.c: Likewise. * sysdeps/powerpc/fpu/s_fdimf.c: Likewise. * sysdeps/powerpc/powerpc32/fpu/s_fdim.c: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_fdim.c: Likewise. * sysdeps/x86_64/fpu/s_fdiml.S: Likewise. * math/libm-test.inc (fdim_test_data): Expect errno setting on overflow. Add sNaN tests.
* powerpc: strcasecmp/strncasecmp optmization for power8raji2016-06-1411-49/+598
| | | | | | | This implementation utilizes vectors to improve performance compared to current byte by byte implementation for POWER7. The performance improvement is upto 4x. This patch is tested on powerpc64 and powerpc64le.
* powerpc: Fix --disable-multi-arch build on POWER8Tulio Magno Quites Machado Filho2016-06-065-6/+27
| | | | | | Add missing symbols of stpncpy and strcasestr when multi-arch is disabled. Fix memset call from strncpy/stpncpy when multi-arch is disabled.
* Fix powerpc64 ceil, rint etc. on sNaN input (bug 20160).Joseph Myers2016-05-2712-12/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | The powerpc64 versions of ceil, floor, round, trunc, rint, nearbyint and their float versions return sNaN for sNaN input when they should return qNaN. This patch fixes them to add a NaN argument to itself to quiet sNaNs before returning. Tested for powerpc64. [BZ #20160] * sysdeps/powerpc/powerpc64/fpu/s_ceil.S (__ceil): Add NaN argument to itself before returning the result. * sysdeps/powerpc/powerpc64/fpu/s_ceilf.S (__ceilf): Likewise. * sysdeps/powerpc/powerpc64/fpu/s_floor.S (__floor): Likewise. * sysdeps/powerpc/powerpc64/fpu/s_floorf.S (__floorf): Likewise. * sysdeps/powerpc/powerpc64/fpu/s_nearbyint.S (__nearbyint): Likewise. * sysdeps/powerpc/powerpc64/fpu/s_nearbyintf.S (__nearbyintf): Likewise. * sysdeps/powerpc/powerpc64/fpu/s_rint.S (__rint): Likewise. * sysdeps/powerpc/powerpc64/fpu/s_rintf.S (__rintf): Likewise. * sysdeps/powerpc/powerpc64/fpu/s_round.S (__round): Likewise. * sysdeps/powerpc/powerpc64/fpu/s_roundf.S (__roundf): Likewise. * sysdeps/powerpc/powerpc64/fpu/s_trunc.S (__trunc): Likewise. * sysdeps/powerpc/powerpc64/fpu/s_truncf.S (__truncf): Likewise.
* Fix powerpc32 ceil, rint etc. on sNaN input (bug 20160).Joseph Myers2016-05-2712-12/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | The powerpc32 versions of ceil, floor, round, trunc, rint, nearbyint and their float versions return sNaN for sNaN input when they should return qNaN. This patch fixes them to add a NaN argument to itself to quiet sNaNs before returning. The powerpc64 versions, which have the same bug, will be addressed separately. Tested for powerpc32. [BZ #20160] * sysdeps/powerpc/powerpc32/fpu/s_ceil.S (__ceil): Add NaN argument to itself before returning the result. * sysdeps/powerpc/powerpc32/fpu/s_ceilf.S (__ceilf): Likewise. * sysdeps/powerpc/powerpc32/fpu/s_floor.S (__floor): Likewise. * sysdeps/powerpc/powerpc32/fpu/s_floorf.S (__floorf): Likewise. * sysdeps/powerpc/powerpc32/fpu/s_nearbyint.S (__nearbyint): Likewise. * sysdeps/powerpc/powerpc32/fpu/s_nearbyintf.S (__nearbyintf): Likewise. * sysdeps/powerpc/powerpc32/fpu/s_rint.S (__rint): Likewise. * sysdeps/powerpc/powerpc32/fpu/s_rintf.S (__rintf): Likewise. * sysdeps/powerpc/powerpc32/fpu/s_round.S (__round): Likewise. * sysdeps/powerpc/powerpc32/fpu/s_roundf.S (__roundf): Likewise. * sysdeps/powerpc/powerpc32/fpu/s_trunc.S (__trunc): Likewise. * sysdeps/powerpc/powerpc32/fpu/s_truncf.S (__truncf): Likewise.
* Avoid "invalid" exceptions from powerpc fabsl (sNaN) (bug 20157).Joseph Myers2016-05-272-5/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The powerpc implementations of fabsl for ldbl-128ibm (both powerpc32 and powerpc64) wrongly raise the "invalid" exception for sNaN arguments. fabs functions should be quiet for all inputs including signaling NaNs. The problem is the use of a comparison instruction fcmpu to determine if the high part of the argument is negative and so the low part needs to be negated; such instructions raise "invalid" for sNaNs. There is a pure integer implementation of fabsl in sysdeps/ieee754/ldbl-128ibm/s_fabsl.c. However, it's not necessary to use it to avoid such exceptions. The fsel instruction does not raise exceptions for sNaNs, and can be used in place of the original comparison. (Note that if the high part is zero or a NaN, it does not matter whether the low part is negated; the choice of whether the low part of a zero is +0 or -0 does not affect the value, and the low part of a NaN does not affect the value / payload either.) The condition in GCC for fsel to be available is TARGET_PPC_GFXOPT, corresponding to the _ARCH_PPCGR predefined macro. fsel is available on all 64-bit processors supported by GCC. A few 32-bit processors supported by GCC do not have TARGET_PPC_GFXOPT despite having hard float support. To support those processors, integer code (similar to that in copysignl) is included for the !_ARCH_PPCGR case for powerpc32. Tested for powerpc32 (configurations with and without _ARCH_PPCGR) and powerpc64. [BZ #20157] * sysdeps/powerpc/powerpc32/fpu/s_fabsl.S (__fabsl): Use fsel to determine whether to negate low half if [_ARCH_PPCGR], and integer comparison otherwise. * sysdeps/powerpc/powerpc64/fpu/s_fabsl.S (__fabsl): Use fsel to determine whether to negate low half.
* Do not raise "inexact" from powerpc64 ceil, floor, trunc (bug 15479).Joseph Myers2016-05-256-18/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Continuing fixes for ceil, floor and trunc functions not to raise the "inexact" exception, this patch fixes the versions used on older powerpc64 processors. As was done with the round implementations some time ago, the save of floating-point state is moved after the first floating-point operation on the input to ensure that any "invalid" exception from signaling NaN input is included in the saved state, and then the whole state gets restored rather than just the rounding mode. This has no effect on configurations using the power5+ code, since such processors can do these operations with a single instruction (and those instructions do not set "inexact", so are correct for TS 18661-1 semantics). Tested for powerpc64. [BZ #15479] * sysdeps/powerpc/powerpc64/fpu/s_ceil.S (__ceil): Move save of floating-point state after first floating-point operation on input. Restore full floating-point state instead of just rounding mode. * sysdeps/powerpc/powerpc64/fpu/s_ceilf.S (__ceilf): Likewise. * sysdeps/powerpc/powerpc64/fpu/s_floor.S (__floor): Likewise. * sysdeps/powerpc/powerpc64/fpu/s_floorf.S (__floorf): Likewise. * sysdeps/powerpc/powerpc64/fpu/s_trunc.S (__trunc): Likewise. * sysdeps/powerpc/powerpc64/fpu/s_truncf.S (__truncf): Likewise.
* Do not raise "inexact" from powerpc32 ceil, floor, trunc (bug 15479).Joseph Myers2016-05-256-18/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Continuing fixes for ceil, floor and trunc functions not to raise the "inexact" exception, this patch fixes the versions used on older powerpc32 processors. As was done with the round implementations some time ago, the save of floating-point state is moved after the first floating-point operation on the input to ensure that any "invalid" exception from signaling NaN input is included in the saved state, and then the whole state gets restored rather than just the rounding mode. This has no effect on configurations using the power5+ code, since such processors can do these operations with a single instruction (and those instructions do not set "inexact", so are correct for TS 18661-1 semantics). Tested for powerpc32. [BZ #15479] * sysdeps/powerpc/powerpc32/fpu/s_ceil.S (__ceil): Move save of floating-point state after first floating-point operation on input. Restore full floating-point state instead of just rounding mode. * sysdeps/powerpc/powerpc32/fpu/s_ceilf.S (__ceilf): Likewise. * sysdeps/powerpc/powerpc32/fpu/s_floor.S (__floor): Likewise. * sysdeps/powerpc/powerpc32/fpu/s_floorf.S (__floorf): Likewise. * sysdeps/powerpc/powerpc32/fpu/s_trunc.S (__trunc): Likewise. * sysdeps/powerpc/powerpc32/fpu/s_truncf.S (__truncf): Likewise.
* powerpc: Fix operand prefixesGabriel F. T. Gomes2016-05-041-4/+4
| | | | | | | | | | | | | | The file sysdeps/powerpc/sysdeps.h defines aliases for condition register operands. E.g.: 'cr7' means condition register 7. On the one hand, this increases readability, as it makes it easier for readers to know whether the operand is a condition register, a general purpose register or an immediate. On the other hand, this permits that condition registers be written as if they were general purpose, and vice-versa, thus reducing the readability of the code. This commit removes some of these unintentional misuses. The changes have no effect on the final code. Checked with objdump.
* powerpc: Zero pad using memset in strncpy/stpncpyGabriel F. T. Gomes2016-04-291-67/+56
| | | | | | | Call __memset_power8 to pad, with zeros, the remaining bytes in the dest string on __strncpy_power8 and __stpncpy_power8. This improves performance when n is larger than the input string, giving ~30% gain for larger strings without impacting much shorter strings.
* powerpc: Add optimized strcspn for P8Paul E. Murphy2016-04-258-29/+151
| | | | | A few minor adjustments to the P8 strspn gives us an almost equally optimized P8 strcspn.
* powerpc: strcasestr optmization for power8Rajalakshmi Srinivasaraghavan2016-04-229-1/+697
| | | | | | This patch optimizes strcasestr function for power >= 8 systems. The average improvement of this optimization is ~40% and compares 16 bytes at a time using vector instructions. This patch is tested on powerpc64 and powerpc64le.
* powerpc: Optimization for strlen for POWER8.Carlos Eduardo Seo2016-04-155-4/+345
| | | | | This implementation takes advantage of vectorization to improve performance of the loop over the current strlen implementation for POWER7.
* powerpc: Add optimized P8 strspnPaul E. Murphy2016-04-076-1/+289
| | | | | | | This utilizes vectors and bitmasks. For small needle, large haystack, the performance improvement is upto 8x. For short strings (0-4B), the cost of computing the bitmask dominates, and is a tad slower.
* Remove powerpc64 strspn, strcspn, and strpbrk implementationAdhemerval Zanella2016-04-013-406/+0
| | | | | | | | | | | | | This patch removes the powerpc64 optimized strspn, strcspn, and strpbrk assembly implementation now that the default C one implements the same strategy. On internal glibc benchtests current implementations shows similar performance with -O2. Tested on powerpc64le (POWER8). * sysdeps/powerpc/powerpc64/strcspn.S: Remove file. * sysdeps/powerpc/powerpc64/strpbrk.S: Remove file. * sysdeps/powerpc/powerpc64/strspn.S: Remove file.
* powerpc: Rearrange cfi_offset callsRajalakshmi Srinivasaraghavan2016-03-116-34/+34
| | | | | This patch rearranges cfi_offset() calls after the last store so as to avoid extra DW_CFA_advance opcodes in unwind information.
* Fix ldbl-128ibm nearbyintl in non-default rounding modes (bug 19790).Joseph Myers2016-03-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ldbl-128ibm implementation of nearbyintl uses logic that only works in round-to-nearest mode. This contrasts with rintl, which works in all rounding modes. Now, arguably nearbyintl could simply be aliased to rintl, given that spurious "inexact" is generally allowed for ldbl-128ibm, even for the underlying arithmetic operations. But given that the only point of nearbyintl is to avoid "inexact", this patch follows the more conservative approach of adding conditionals to the rintl implementation to make it suitable for use to implement nearbyintl, then builds it for nearbyintl with USE_AS_NEARBYINTL defined. The test test-nearbyint-except-2 shows up issues when traps on "inexact" are enabled, which turn out to be problems with the powerpc fenv_private.h implementation (two functions that should disable exception traps potentially failing to do so in some cases); this patch duly fixes that as well (I don't see any other existing cases where this would be user-visible; there isn't much use of *_NOEX, *hold* etc. in libm that requires exceptions to be discarded and not trapped on). Tested for powerpc. [BZ #19790] * sysdeps/ieee754/ldbl-128ibm/s_rintl.c [USE_AS_NEARBYINTL] (rintl): Define as macro. [USE_AS_NEARBYINTL] (__rintl): Likewise. (__rintl) [USE_AS_NEARBYINTL]: Use SET_RESTORE_ROUND_NOEX instead of fesetround. Ensure results are evaluated before end of scope. * sysdeps/ieee754/ldbl-128ibm/s_nearbyintl.c: Define USE_AS_NEARBYINTL and include s_rintl.c. * sysdeps/powerpc/fpu/fenv_private.h (libc_feholdsetround_ppc): Disable exception traps in new environment. (libc_feholdsetround_ppc_ctx): Likewise.
* powerpc: Remove uses of operand modifier (%s) in inline asmGabriel F. T. Gomes2016-03-081-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The operand modifier %s on powerpc is an undocumented internal implementation detail of GCC. Besides that, the GCC community wants to remove it. This patch rewrites the expressions that use this modifier with logically equivalent expressions that don't require it. Explanation for the substitution: The %s modifier takes an immediate operand and prints 32 less such immediate. Thus, in the previous code, the expression resulted in: 32 - __builtin_ffs(e) where e was guaranteed to have exactly a single bit set, by the following expressions: (e & (e-1) == 0) : e has at most one bit set. (e != 0) : e is not zero, thus it has at least one bit set. Since we guarantee that there is exactly only one bit set, the following statement is true: 32 - __builtin_ffs(e) == __builtin_clz(e) Thus, we can replace __builtin_ffs with __builtin_clz and remove the %s operand modifier.
* powerpc: Fix dl-procinfo HWCAPCarlos Eduardo Seo2016-03-082-8/+6
| | | | | | HWCAP-related code should had been updated when the 32 bits of HWCAP were used. This patch updates the code in dl-procinfo.h to loop through all the 32 bits in HWCAP and updates _dl_powerpc_cap_flags accordingly.
* powerpc: Regenerate libm-test-ulpsRajalakshmi Srinivasaraghavan2016-02-041-0/+10
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* Remove unused variablesAndreas Schwab2016-01-272-3/+0
| | | | They are flagged by -Wunused-const-variable.
* Fix ulps regeneration for *-finite tests.Joseph Myers2016-01-191-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On running tests after from-scratch ulps regeneration, I found that some libm tests failed with ulps in excess of those recorded in the from-scratch regeneration, which should never happen unless those ulps exceed the limit on ulps that can go in libm-test-ulps files. Failure: Test: atan2_upward (inf, -inf) Result: is: 2.35619498e+00 0x1.2d97ccp+1 should be: 2.35619450e+00 0x1.2d97c8p+1 difference: 4.76837159e-07 0x1.000000p-21 ulp : 2.0000 max.ulp : 1.0000 Maximal error of `atan2_upward' is : 2 ulp accepted: 1 ulp Failure: Test: carg_upward (-inf + inf i) Result: is: 2.35619498e+00 0x1.2d97ccp+1 should be: 2.35619450e+00 0x1.2d97c8p+1 difference: 4.76837159e-07 0x1.000000p-21 ulp : 2.0000 max.ulp : 1.0000 Maximal error of `carg_upward' is : 2 ulp accepted: 1 ulp The problem comes from the addition of tests for the finite-math-only versions of libm functions. Those tests share ulps with the default function variants. make regen-ulps runs the default tests before the finite-math-only tests, concatenating the resulting ulps before feeding them to gen-libm-test.pl to generate a new libm-test-ulps file. But gen-libm-test.pl always takes the last ulps value given for any (function, type) pair. So, if the largest ulps for a function come from non-finite inputs, a from-scratch regeneration loses those ulps. This patch fixes gen-libm-test.pl, in the case where there are multiple ulps values for a (function, type) pair - which can only happen as part of a regeneration - to take the largest ulps value rather than the last one. Tested for ARM / MIPS / powerpc-nofpu. * math/gen-libm-test.pl (parse_ulps): Do not reduce already-recorded ulps. * sysdeps/arm/libm-test-ulps: Regenerated. * sysdeps/mips/mips32/libm-test-ulps: Likewise. * sysdeps/mips/mips64/libm-test-ulps: Likewise. * sysdeps/powerpc/nofpu/libm-test-ulps: Likewise.
* Regenerate powerpc-nofpu libm-test-ulps.Joseph Myers2016-01-181-210/+230
| | | | * sysdeps/powerpc/nofpu/libm-test-ulps: Regenerated.
* powerpc: Enforce compiler barriers on hardware transactionsTulio Magno Quites Machado Filho2016-01-082-5/+5
| | | | | | | Work around a GCC behavior with hardware transactional memory built-ins. GCC doesn't treat the PowerPC transactional built-ins as compiler barriers, moving instructions past the transaction boundaries and altering their atomicity.
* powerpc: Add hwcap2 bits for POWER9.Carlos Eduardo Seo2016-01-082-1/+4
| | | | | Added hwcap2 bit masks for Power ISA 3.0 and VSX IEEE binary float 128-bit features.
* Update copyright dates with scripts/update-copyrights.Joseph Myers2016-01-04755-755/+755
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* powerpc: Export __parse_hwcap_and_convert_at_platform to libc.a.Carlos Eduardo Seo2015-12-221-0/+8
| | | | | | | | | Commit 67385a01d229751569b6aac067ffdcd813a15d7a added a new feature for powerpc, where we store HWCAP/Platform bits in the TCB. In the dynamic linking case, we use the versioned symbol '__parse_hwcap_and_convert_at_platform' to verify if this feature is available. However, the same symbol was not exported to libc.a, making it not possible for GCC to check for it prior to link time.
* powerpc: Add basic support for POWER9 sans hwcap.Carlos Eduardo Seo2015-12-229-2/+17
| | | | This patch adds the minimum changes for supporting the POWER9 processor.
* powerpc: Regenerate libm-test-ulpsAdhemerval Zanella2015-12-221-169/+199
| | | | * sysdeps/powerpc/fpu/libm-test-ulps: Regenerated.
* Fix POWER7 logb results for negative subnormals (bug 19375)Adhemerval Zanella2015-12-171-0/+1
| | | | | | | | | | | | | | | | The optimized POWER7 logb implementation does not use the absolute value of the word extracted from the input to apply the leading 0-bits builtin (to ignore the float sign). This patch fixes it by clearing the signal bit in the resulting word. It fixes the subnormal tests failures when running on POWER7 ou newer chip. Tested on powerpc64le (POWER8). [BZ# 19375] * sysdeps/powerpc/power7/fpu/s_logb.c (__logb): Fix return for negative subnormals.
* powerpc: Add hwcap/hwcap2/platform data to TCB.Carlos Eduardo Seo2015-12-0310-6/+406
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a new feature for powerpc. In order to get faster access to the HWCAP/HWCAP2 bits and platform number (i.e. for implementing __builtin_cpu_is () / __builtin_cpu_supports () in GCC) without the overhead of reading from the auxiliary vector, we now reserve space for them in the TCB. This is an ABI change for GLIBC 2.23. A new versioned symbol '__parse_hwcap_and_convert_at_platform' is available to get the data from the auxiliary vector and parse it, and store it for later use in the TLS initialization code. This function is called very early (in _dl_sysdep_start () via DL_PLATFORM_INFO for the dynamic linking case, and in __libc_start_main () for the static linking case) to make sure the data is available at the time of TLS initialization. * sysdeps/powerpc/Makefile (sysdep-dl-routines): Add hwcapinfo. (sysdep_routines): Likewise. (sysdep-rtld-routines): Likewise. [$(subdir) = nptl](tests): Add test-get_hwcap and test-get_hwcap-static [$(subdir) = nptl](tests-static): test-get_hwcap-static * sysdeps/powerpc/Versions: Added new __parse_hwcap_and_convert_at_platform symbol to GLIBC-2.23. * sysdeps/powerpc/hwcapinfo.c: New file. (__tcb_parse_hwcap_and_convert_at_platform): New function to initialize and parse hwcap, hwcap2 and platform number information. * sysdeps/powerpc/hwcapinfo.h: New file. Creates global variables to store HWCAP+HWCAP2 and platform number. * sysdeps/powerpc/nptl/tcb-offsets.sym: Added new offsets for HWCAP+HWCAP2 and platform number in the TCB. * sysdeps/powerpc/nptl/tls.h: New functionality. Stores the HWCAP, HWCAP2 and platform number in the TCB. (dtv): Added new fields for HWCAP+HWCAP2 and platform number. (TLS_INIT_TP): Included calls to add the hwcap and at_platform values in the TCB in TP initialization. (TLS_DEFINE_INIT_TP): Likewise. (THREAD_GET_HWCAP): New macro. (THREAD_SET_HWCAP): Likewise. (THREAD_GET_AT_PLATFORM): Likewise. (THREAD_SET_AT_PLATFORM): Likewise. * sysdeps/powerpc/powerpc32/dl-machine.h: (dl_platform_init): New function that calls __parse_hwcap_and_convert_at_platform for the dymanic linking case for powerpc32. * sysdeps/powerpc/powerpc64/dl-machine.h: Likewise, for powerpc64. * sysdeps/powerpc/test-get_hwcap-static.c: New file. Testcase for this functionality, static linking case. * sysdeps/powerpc/test-get_hwcap.c: New file. Likewise, dynamic linking case. * sysdeps/unix/sysv/linux/powerpc/libc-start.c: Added call to __parse_hwcap_and_convert_at_platform for the static linking case. * sysdeps/unix/sysv/linux/powerpc/powerpc32/ld.abilist: Included the new __parse_hwcap_and_convert_at_platform symbol in the ABI list for GLIBC 2.23. * sysdeps/unix/sysv/linux/powerpc/powerpc64/ld-le.abilist: Likewise. * sysdeps/unix/sysv/linux/powerpc/powerpc64/ld.abilist: Likewise.
* powerpc: Spinlock optimization and cleanupPaul Murphy2015-11-193-4/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch optimizes powerpc spinlock implementation by: * Use the correct EH hint bit on the larx for supported ISA. For lock acquisition, the thread that acquired the lock with a successful stcx does not want to give away the write ownership on the cacheline. The idea is to make the load reservation "sticky" about retaining write authority to the line. That way, the store that must inevitably come to release the lock can succeed quickly and not contend with other threads issuing lwarx. If another thread does a store to the line (false sharing), the winning thread must give up write authority to the proper value of EH for the larx for a lock acquisition is 1. * Increase contented lock performance by up to 40%, and no measurable impact on uncontended locks on P8. Thanks to Adhemerval Zanella who did most of the work. I've run some tests, and addressed some minor feedback. * sysdeps/powerpc/nptl/pthread_spin_lock.c (pthread_spin_lock): Add lwarx hint, and use macro for acquire instruction. * sysdeps/powerpc/nptl/pthread_spin_trylock.c (pthread_spin_trylock): Likewise. * sysdep/unix/sysv/linux/powerpc/pthread_spin_unlock.c: Move to ... * sysdeps/powerpc/nptl/pthread_spin_unlock.c: ... here, and update to use new atomic macros.
* Fix powerpc round, roundf spurious "inexact" (bug 19238).Joseph Myers2015-11-124-12/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The powerpc hard-float round and roundf functions, both 32-bit and 64-bit, raise spurious "inexact" exceptions for integer arguments from adding 0.5 and rounding to integer toward zero. Since these functions already save and restore the rounding mode, it's natural to make them restore the full floating-point state instead to fix this bug, which this patch does. The save of the state is moved after the first floating-point operation on the input so that any "invalid" exceptions from signaling NaN inputs are properly preserved. As a consequence of this approach to the fix, "inexact" for noninteger arguments (disallowed by TS 18661-1 but not by C99/C11, see bug 15479) is also avoided for these implementations; this is *not* a general fix for bug 15479 since plenty of other implementations of various functions still raise spurious "inexact" for noninteger arguments. This issue and fix do not apply to builds using power5+ versions of round and roundf, which use the frin instruction and avoid "inexact" exceptions that way. This patch should get hard-float powerpc32 and powerpc64 (default function implementations) back to a state where test-float and test-double will pass after ulps regeneration. Tested for powerpc32 and powerpc64. [BZ #15479] [BZ #19238] * sysdeps/powerpc/powerpc32/fpu/s_round.S (__round): Save floating-point state after first operation on input. Restore full state rather than just rounding mode. * sysdeps/powerpc/powerpc32/fpu/s_roundf.S (__roundf): Likewise. * sysdeps/powerpc/powerpc64/fpu/s_round.S (__round): Likewise. * sysdeps/powerpc/powerpc64/fpu/s_roundf.S (__roundf): Likewise.
generated by cgit-pink 1.4.1 (git 2.36.1) at 2024-07-25 17:02:22 +0000