Commit message (Collapse) | Author | Age | Files | Lines | |
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* | PowerPC: strncpy/stpncpy optimization for PPC64/POWER7 | Vidya Ranganathan | 2014-05-06 | 1 | -0/+16 |
| | | | | | | | | The optimization is achieved by following techniques: > data alignment [gain from aligned memory access on read/write] > POWER7 gains performance with loop unrolling/unwinding [gain by reduction of branch penalty]. > zero padding done by calling optimized memset | ||||
* | PowerPC: optimized strpbrk for POWER7 | Adhemerval Zanella | 2014-03-20 | 1 | -0/+8 |
| | | | | | | | | | This patch add an optimized strpbrk for POWER7 by using a different algorithm than default implementation: it constructs a table based on the 'accept' argument and use this table to check for any occurance on the input string. The idea is similar as x86_64 uses. For PowerPC some tunings were added, such as unroll loops and memory clear using VSX instructions. | ||||
* | PowerPC: optimized strcspn for PPC64/POWER7 | Adhemerval Zanella | 2014-03-20 | 1 | -0/+8 |
| | | | | | | | | | | This patch add a optimized strcspn for POWER7 by using a different algorithm than default implementation: it constructs a table based on the 'accept' argument and use this table to check for any occurance on the input string. The idea is similar as x86_64 uses. For PowerPC some tunings were added, such as unroll loops and align stack memory to table to 16 bytes (so VSX clean can ran without alignment issues). | ||||
* | PowerPC: strspn optimization for PPC64/POWER7 | Vidya Ranganathan | 2014-03-11 | 1 | -0/+8 |
| | | | | | | | | The optimization is achieved by following techniques: > hashing of needle. > hashing avoids scanning of duplicate entries in needle across the string. > initializing the hash table with Vector instructions (VSX) by quadword access. > unrolling when scanning for character in string across hash table. | ||||
* | PowerPC: strncat optimization for PPC64 | Adhemerval Zanella | 2014-03-10 | 1 | -0/+8 |
| | | | | | | | | The optimization is achieved by following techniques: 1. Doubleword aligned memory access and compares using cmpb instruction. 2. Loop unrolling for byte load/store. 3. CPU pre-fetch to avoid cache miss. | ||||
* | PowerPC: strrchr optimization for POWER7/PPC64 | Rajalakshmi Srinivasaraghavan | 2014-03-03 | 1 | -0/+8 |
| | | | | | | This patch optimizes strrchr() for ppc64. It uses aligned memory access along with cmpb instruction and CPU prefetch to avoid cache misses for speed improvement. | ||||
* | Update copyright notices with scripts/update-copyrights | Allan McRae | 2014-01-01 | 1 | -1/+1 |
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* | PowerPC: multiarch stpcpy for PowerPC64 | Adhemerval Zanella | 2013-12-13 | 1 | -0/+7 |
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* | PowerPC: multiarch strcpy for PowerPC64 | Adhemerval Zanella | 2013-12-13 | 1 | -0/+7 |
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* | PowerPC: multiarch wcscpy for PowerPC64. | Adhemerval Zanella | 2013-12-13 | 1 | -0/+11 |
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* | PowerPC: multiarch wcsrchr for PowerPC64 | Adhemerval Zanella | 2013-12-13 | 1 | -0/+11 |
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* | PowerPC: multiarch wcschr for PowerPC64 | Adhemerval Zanella | 2013-12-13 | 1 | -0/+11 |
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* | PowerPC: multiarch strchrnul for PowerPC64 | Adhemerval Zanella | 2013-12-13 | 1 | -0/+8 |
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* | PowerPC: multiarch strchr for PowerPC64 | Adhemerval Zanella | 2013-12-13 | 1 | -0/+8 |
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* | PowerPC: multiarch strncmp for PowerPC64 | Adhemerval Zanella | 2013-12-13 | 1 | -0/+9 |
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* | PowerPC: multiarch strncasecmp for PowerPC64 | Adhemerval Zanella | 2013-12-13 | 1 | -0/+15 |
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* | PowerPC: multiarch strcasecmp for PowerPC64 | Adhemerval Zanella | 2013-12-13 | 1 | -0/+15 |
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* | PowerPC: multiarch strnlen for PowerPC64 | Adhemerval Zanella | 2013-12-13 | 1 | -0/+7 |
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* | PowerPC: multiarch strlen for PowerPC64 | Adhemerval Zanella | 2013-12-13 | 1 | -0/+7 |
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* | PowerPC: multiarch rawmemchr for PowerPC64 | Adhemerval Zanella | 2013-12-13 | 1 | -0/+8 |
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* | PowerPC: multiarch memrchr for PowerPC64 | Adhemerval Zanella | 2013-12-13 | 1 | -0/+8 |
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* | PowerPC: multiarch memchr for PowerPC64 | Adhemerval Zanella | 2013-12-13 | 1 | -0/+8 |
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* | PowerPC: multiarch mempcpy for PowerPC64 | Adhemerval Zanella | 2013-12-13 | 1 | -0/+8 |
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* | PowerPC: multiarch memset/bzero for PowerPC64 | Adhemerval Zanella | 2013-12-13 | 1 | -0/+20 |
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* | PowerPC: multirach memcmp for PowerPC64 | Adhemerval Zanella | 2013-12-13 | 1 | -0/+8 |
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* | PowerPC: multiarch memcpy for PowerPC64 | Adhemerval Zanella | 2013-12-13 | 1 | -0/+66 |