| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | aarch64: Add half-width versions of AdvSIMD f32 libmvec routines | Joe Ramsay | 2023-12-20 | 1 | -1/+3 |
| | | | | | | | | | | | | Compilers may emit calls to 'half-width' routines (two-lane single-precision variants). These have been added in the form of wrappers around the full-width versions, where the low half of the vector is simply duplicated. This will perform poorly when one lane triggers the special-case handler, as there will be a redundant call to the scalar version, however this is expected to be rare at Ofast. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com> | ||||
| * | aarch64: Add vector implementations of exp10 routines | Joe Ramsay | 2023-10-23 | 1 | -0/+140 |
| Double-precision routines either reuse the exp table (AdvSIMD) or use SVE FEXPA intruction. | |||||
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