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* [AArch64] Fix BE access to errno.Andrew Pinski2013-09-302-1/+6
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* [AArch64] Support __mcount profiling.Marcus Shawcroft2013-09-242-8/+12
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* [AArch64] Adding sigcontextinfo.hMarcus Shawcroft2013-09-242-0/+39
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* ports/sysdeps/arm/nptl/tls.h: Remove TLS_INIT_TP_EXPENSIVE.Will Newton2013-09-242-4/+5
| | | | | | | | | | | This define was removed from the rest of the tree eight years ago. ports/ChangeLog.arm: 2013-09-24 Will Newton <will.newton@linaro.org> * ports/sysdeps/arm/nptl/tls.h (TLS_INIT_TP_EXPENSIVE): Remove macro.
* 2013-09-23 Steve Ellcey <sellcey@mips.com>Steve Ellcey2013-09-232-0/+131
| | | | | | | | | | | | | | | | | | | | | | | * sysdeps/mips/math_private.h (libc_feholdexcept_mips): New function. (libc_feholdexcept): New macro. (libc_feholdexceptf): New macro. (libc_feholdexceptl): New macro. (libc_fesetround_mips): New function. (libc_fesetround): New macro. (libc_fesetroundf): New macro. (libc_fesetroundl): New macro. (libc_feholdexcept_setround_mips): New function. (libc_feholdexcept_setround): New macro. (libc_feholdexcept_setroundf): New macro. (libc_feholdexcept_setroundl): New macro. (libc_fesetenv_mips): New function. (libc_fesetenv): New macro. (libc_fesetenvf): New macro. (libc_fesetenvl): New macro. (libc_feupdateenv_mips): New function. (libc_feupdateenv): New macro. (libc_feupdateenvf): New macro. (libc_feupdateenvl): New macro.
* MIPS: bits/atomic.h: Fix comment typoMaciej W. Rozycki2013-09-232-1/+5
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* 2013-09-23 Steve Ellcey <sellcey@mips.com>Steve Ellcey2013-09-233-3/+8
| | | | | * sysdeps/mips/fpu/fegetround.c (fegetround): Use _FPU_RC_MASK. * sysdeps/mips/fpu/fesetround.c (fesetround): Use _FPU_RC_MASK.
* 2013-09-19 Steve Ellcey <sellcey@mips.com>Steve Ellcey2013-09-232-0/+6
| | | | * sysdeps/mips/fpu_control.h (_FPU_RC_MASK): New.
* 2013-09-23 Steve Ellcey <sellcey@mips.com>Steve Ellcey2013-09-232-3/+8
| | | | | * sysdeps/mips/fpu_control.h (comments): Add capitalization and periods to match GNU standard.
* BZ #15754: CVE-2013-4788Carlos O'Donell2013-09-234-0/+19
| | | | | | | | | | | | The pointer guard used for pointer mangling was not initialized for static applications resulting in the security feature being disabled. The pointer guard is now correctly initialized to a random value for static applications. Existing static applications need to be recompiled to take advantage of the fix. The test tst-ptrguard1-static and tst-ptrguard1 add regression coverage to ensure the pointer guards are sufficiently random and initialized to a default value.
* Make __ffs hiddenAndreas Schwab2013-09-209-0/+22
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* Remove trailing space.Steve Ellcey2013-09-201-1/+1
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* 2013-09-20 Steve Ellcey <sellcey@mips.com>Steve Ellcey2013-09-201-90/+0
| | | | | * sysdeps/mips/memset.S: Change prefetching and add loop unrolling. * sysdeps/mips/mips64/memset.S: Remove.
* 2013-09-20 Steve Ellcey <sellcey@mips.com>Steve Ellcey2013-09-202-56/+343
| | | | | * sysdeps/mips/memset.S: Change prefetching and add loop unrolling. * sysdeps/mips/mips64/memset.S: Remove.
* Improve atomic locking for ARM.Maxim Kuvyrkov2013-09-192-8/+96
| | | | | | | | | | [BZ #15640] * sysdeps/arm/bits/atomic.h (atomic_exchange_acq, atomic_exchange_rel) (atomic_compare_and_exchange_bool_acq) (atomic_compare_and_exchange_val_acq) (atomic_compare_and_exchange_bool_rel) (atomic_compare_and_exchange_val_rel): Use __atomic_exchange_n and __atomic_compare_exchange_n builtins when GCC supports them.
* MIPS: IEEE 754-2008 NaN encoding supportMaciej W. Rozycki2013-09-1815-50/+640
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It has been a long practice for software using IEEE 754 floating-point arithmetic run on MIPS processors to use an encoding of Not-a-Number (NaN) data different to one used by software run on other processors. And as of IEEE 754-2008 revision [1] this encoding does not follow one recommended in the standard, as specified in section 6.2.1, where it is stated that quiet NaNs should have the first bit (d1) of their significand set to 1 while signalling NaNs should have that bit set to 0, but MIPS software interprets the two bits in the opposite manner. As from revision 3.50 [2][3] the MIPS Architecture provides for processors that support the IEEE 754-2008 preferred NaN encoding format. As the two formats (further referred to as "legacy NaN" and "2008 NaN") are incompatible to each other, tools have to provide support for the two formats to help people avoid using incompatible binary modules. The change is comprised of two functional groups of features, both of which are required for correct support. 1. Dynamic linker support. To enforce the NaN encoding requirement in dynamic linking a new ELF file header flag has been defined. This flag is set for 2008-NaN shared modules and executables and clear for legacy-NaN ones. The dynamic linker silently ignores any incompatible modules it encounters in dependency processing. To avoid unnecessary processing of incompatible modules in the presence of a shared module cache, a set of new cache flags has been defined to mark 2008-NaN modules for the three ABIs supported. Changes to sysdeps/unix/sysv/linux/mips/readelflib.c have been made following an earlier code quality suggestion made here: http://sourceware.org/ml/libc-ports/2009-03/msg00036.html and are therefore a little bit more extensive than the minimum required. Finally a new name has been defined for the dynamic linker so that 2008-NaN and legacy-NaN binaries can coexist on a single system that supports dual-mode operation and that a legacy dynamic linker that does not support verifying the 2008-NaN ELF file header flag is not chosen to interpret a 2008-NaN binary by accident. 2. Floating environment support. IEEE 754-2008 features are controlled in the Floating-Point Control and Status (FCSR) register and updates are needed to floating environment support so that the 2008-NaN flag is set correctly and the kernel default, inferred from the 2008-NaN ELF file header flag at the time an executable is loaded, respected. As the NaN encoding format is a property of GCC code generation that is both a user-selected GCC configuration default and can be overridden with GCC options, code that needs to know what NaN encoding standard it has been configured for checks for the __mips_nan2008 macro that is defined internally by GCC whenever the 2008-NaN mode has been selected. This mode is determined at the glibc configuration time and therefore a few consistency checks have been added to catch cases where compilation flags have been overridden by the user. The 2008 NaN set of features relies on kernel support as the in-kernel floating-point emulator needs to be aware of the NaN encoding used even on hard-float processors and configure the FPU context according to the value of the 2008 NaN ELF file header flag of the executable being started. As at this time work on kernel support is still in progress and the relevant changes have not made their way yet to linux.org master repository. Therefore the minimum version supported has been artificially set to 10.0.0 so that 2008-NaN code is not accidentally run on a Linux kernel that does not suppport it. It is anticipated that the version is adjusted later on to the actual initial linux.org kernel version to support this feature. Legacy NaN encoding support is unaffected, older kernel versions remain supported. [1] "IEEE Standard for Floating-Point Arithmetic", IEEE Computer Society, IEEE Std 754-2008, 29 August 2008 [2] "MIPS Architecture For Programmers, Volume I-A: Introduction to the MIPS32 Architecture", MIPS Technologies, Inc., Document Number: MD00082, Revision 3.50, September 20, 2012 [3] "MIPS Architecture For Programmers, Volume I-A: Introduction to the MIPS64 Architecture", MIPS Technologies, Inc., Document Number: MD00083, Revision 3.50, September 20, 2012
* ARM: Improve armv7 memcpy performance.Will Newton2013-09-162-6/+10
| | | | | | | | | | | | | | Only enter the aligned copy loop with buffers that can be 8-byte aligned. This improves performance slightly on Cortex-A9 and Cortex-A15 cores for large copies with buffers that are 4-byte aligned but not 8-byte aligned. ports/ChangeLog.arm: 2013-09-16 Will Newton <will.newton@linaro.org> * sysdeps/arm/armv7/multiarch/memcpy_impl.S: Tighten check on entry to aligned copy loop to improve performance.
* Add O_TMPFILE to <fcntl.h>Andreas Schwab2013-09-114-0/+11
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* Define MMAP2_PAGE_SHIFT to -1 for m68k.Joseph Myers2013-09-042-0/+9
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* hppa: add fanotify_markMike Frysinger2013-09-023-0/+11
| | | | | | | | | | | | | | | | | | | Another example of all the 64bit arches getting the definition via a common file, but the 32bit ones all adding it by themselves and hppa was missed. I'm not entirely sure about the usage of GLIBC_2.19 symbols here. We'd like to backport this so people can use it, but it means we'd be releasing a glibc-2.17/glibc-2.18 with a GLIBC_2.19 symbol in it. But maybe it won't be a big deal since you'd only get that 2.19 ref if you actually used the symbol ? There hasn't been a glibc release where hppa worked w/out a bunch of patches, so in reality there's only two distros that matter -- Gentoo and Debian. Reported-by: Jeroen Roovers <jer@gentoo.org> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Use sfi_* macros in armv6t2 strlen.Roland McGrath2013-08-302-9/+16
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* Make armv6t2 strlen work in ARM mode too.Roland McGrath2013-08-302-2/+30
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* Fix then/than typos.Ondřej Bílka2013-08-304-8/+16
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* Fix typos.Ondřej Bílka2013-08-3016-16/+41
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* ARM: Fix clone code when built for Thumb.Will Newton2013-08-302-2/+8
| | | | | | | | | | | | | The mov lr, pc instruction will lose the Thumb bit from the return address so use blx lr instead. ports/ChangeLog.arm: 2013-08-30 Will Newton <will.newton@linaro.org> [BZ #15909] * sysdeps/unix/sysv/linux/arm/clone.S (__clone): Use blx instead of mov lr, pc.
* sysdeps/arm/armv6t2/strlen.S: strlen implementation for armv6t2.Will Newton2013-08-302-0/+145
| | | | | | | | | | | This implementation of strlen is faster than the armv6 version for all string lengths greater than 1 on a Cortex-A15. ports/ChangeLog.arm: 2013-08-09 Will Newton <will.newton@linaro.org> * sysdeps/arm/armv6t2/strlen.S: New file.
* Use ELFOSABI_GNU instead of ELFOSABI_LINUX.Thomas Schwinge2013-08-294-5/+16
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* Fix typos.Ondřej Bílka2013-08-2912-49/+67
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* ARM: Pass dl_hwcap to IFUNC resolver.Carlos O'Donell2013-08-292-1/+8
| | | | | For REL relocs pass dl_hwcap to the IFUNC resolver as is required by the IFUNC API (bug 15905).
* MIPS: Correct the handling of reserved FCSR bitsMaciej W. Rozycki2013-08-224-4/+12
| | | | | | | | | | | | | | | | | | | | Reserved bits in the Floating-Point Control and Status Register (FCSR) should not be implicitly cleared by fedisableexcept or feenableexcept, there is no reason to. Among these are the 8 condition codes and one of the two bits reserved for architecture implementers (bits #22 & #21). As to the latter, there is no reason to treat any of them as reserved either, they should be user controllable and settable via __fpu_control override as the user sees fit. For example in processors implemented by MIPS Technologies, such as the 5Kf or the 24Kf, these bits are used to change the treatment of denormalised operands and tiny results: bit #22 is Flush Override (FO) and bit #21 is Flush to Nearest (FN). They cause non-IEEE-compliant behaviour, but some programs may have a use for such modes of operation; the library should not obstruct such use just as it does not for the architectural Flush to Zero (FS) bit (bit #24). Therefore the change adjusts the reserved mask accordingly and also documents the distinction between bits 22:21 and 20:18.
* Fix typos.Ondřej Bílka2013-08-2117-15/+42
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* PR 15483Alexandre Oliva2013-08-174-0/+24
| | | | | | | | * sysdeps/powerpc/nofpu/sim-full.c: Add FIXME note about the need for thread-specific variables preserved across signal handlers. * sysdeps/powerpc/nofpu/soft-supp.h: Likewise. * sysdeps/powerpc/soft-fp/sfp-machine.h: Likewise.
* [AArch64] Provide symbol version for _mcount.Marcus Shawcroft2013-07-265-0/+81
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* hppa: Regenerate libm-test-ulps.Carlos O'Donell2013-07-232-0/+43
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* tile BZ #15759: Fix bug in _dl_unmapChris Metcalf2013-07-222-3/+15
| | | | | | We returned without calling __munmap if not in the simulator. Now we call a separate sim_dlclose() function to make the control flow work correctly.
* m68k: use _dl_static_init to set GLR0(dl_pagesize)Andreas Schwab2013-07-215-2/+134
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* tile: add missing semicolon in <bits/ptrace.h>Chris Metcalf2013-07-192-1/+6
| | | | | | Change 521c6785e1fc94d added the enum but missed the semicolon. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
* [AArch64] Adding -funwind-tables to backtrace.cMarcus Shawcroft2013-07-122-0/+8
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* [AArch64] Use _dl_static_init to set GLR0(dl_pagesize)Marcus Shawcroft2013-07-095-0/+136
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* tile: use _dl_static_init to set GLRO(gl_pagesize)Chris Metcalf2013-07-075-0/+134
| | | | | | A recently-added test (dlfcn/tststatic5) pointed out that tile was not properly initializing the variable pagesize in certain cases. This change just copies the existing code from MIPS.
* tile: update libm-test-ulps from scratchChris Metcalf2013-07-072-129/+2797
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* tile: use soft-fp for fma() and fmaf()Chris Metcalf2013-07-074-8/+105
| | | | | | The sfp-machine.h is based on the gcc version, but extended with required new macros by comparison with other architectures and by investigating the hardware support for FP on tile.
* [AArch64] Regenerate libm-test-ulpsMarcus Shawcroft2013-07-052-0/+50
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* Sync sys/ptrace with Linux 3.10Andreas Jaeger2013-07-046-3/+102
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* Condition sysdeps/arm/include/bits/setjmp.h contents on _ISOMAC.Joseph Myers2013-07-032-2/+10
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* Regenerate powerpc-nofpu ULPs.Joseph Myers2013-07-032-183/+4158
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* m68k: update libm test ULPsAndreas Schwab2013-07-032-6/+708
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* Regenerate MIPS ulps.Joseph Myers2013-07-023-378/+9206
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* Regenerate ARM ulps.Joseph Myers2013-07-022-103/+2806
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* Make soft-float ARM use soft-fp fma/fmaf.Joseph Myers2013-07-025-0/+69
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