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* Fix dbl-64 e_sqrt.c for non-default rounding modes (bug 16271).Joseph Myers2013-11-2818-0/+48
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* MIPS: Fix RLIM64_INFINITY constant for O32 and N32 ABIsAurelien Jarno2013-11-278-30/+75
| | | | | | | Fix the RLIM64_INFINITY constant for O32 and N32 ABIs to match the kernel one. Change the getrlimit64/setrlimit64 into old compat symbols, and provide the Linux generic getrlimit64/setrlimit64 functions as GLIBC_2_19 version.
* MIPS: Add wrappers to get/setrlimit64 to fix RLIM64_INFINITY constantAurelien Jarno2013-11-273-0/+127
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RLIM64_INFINITY was supposed to be a glibc convention rather than anything seen by the kernel, but it ended being passed to the kernel through the prlimit64 syscall. On O32 and N32 ABIs, we therefore end-up with different values on the userland and kernel side: * On the kernel side, the value is defined for all architectures as include/uapi/linux/resource.h: #define RLIM64_INFINITY (~0ULL) * On the GNU libc side, the value is defined in ports/sysdeps/unix/sysv/linux/mips/bits/resource.h: For the O32 and N32 ABI: # define RLIM64_INFINITY 0x7fffffffffffffffULL and for the N64 ABI: # define RLIM64_INFINITY 0xffffffffffffffffUL This was not a problem until the prlimit64 syscall was wired in the 2.6.36 kernel. Given the GLIBC uses the prlimit64 syscall to implement getrlimit64 and setrlimit64, pam_limits.so is setting the limits to a very big value instead of infinity. As a normal user process can later only decrease the value and not increase it, it will later get and EPERM error when trying to set the value to infinity with setrlimit. The GLIBC has this constant for more than 7 years, and as it is defined in a header file, it means a lot of binaries are in the wild. This patch fixes that by adding a wrapper to fix the value passed to or received from the kernel, before or after calling the prlimit64 syscall.
* aarch64: Enable ifunc support.Will Newton2013-11-263-3/+49
| | | | | | | | | | | | | | | | | Add support for handling the R_AARCH64_IRELATIVE relocation and STT_GNU_IFUNC symbols to the aarch64 port. ports/ChangeLog.aarch64: 2013-11-26 Will Newton <will.newton@linaro.org> * sysdeps/aarch64/dl-irel.h: Include ldsodefs.h. (ELF_MACHINE_IRELA): Define. (elf_ifunc_invoke): Pass hwcap to ifunc resolver function. (elf_irela): New function. * sysdeps/aarch64/dl-machine.h: Include dl-irel.h. (elf_machine_rela) Handle STT_GNU_IFUNC symbols and R_AARCH64_IRELATIVE relocations. (elf_machine_lazy_rel): Handle R_AARCH64_IRELATIVE relocations.
* Use __glibc_reserved instead __unused.Ondřej Bílka2013-11-2636-111/+150
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* ARM: Fix memcpy computed-jump calculations for ARM_ALWAYS_BX case.Roland McGrath2013-11-223-18/+19
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* Don't use broken DL_AUTO_FUNCTION_ADDRESS()Guy Martin2013-11-216-48/+82
| | | | | | | | | | | | On hppa and ia64, the macro DL_AUTO_FUNCTION_ADDRESS() uses the variable fptr[2] in it's own scope. The content of fptr[] is thus undefined right after the macro exits. Newer gcc's (>= 4.7) reuse the stack space of this variable triggering a segmentation fault in dl-init.c:69. To fix this we rewrite the macros to make the call directly to init and fini without needing to pass back a constructed function pointer.
* linux-generic: fix alignment of struct stat/statfs for nios2Chung-Lin Tang2013-11-203-6/+15
| | | | | | | | | The hard alignment of 8 was appropriate for most platforms for which 8-byte values are 8-byte aligned, but this is not true for the nios2 platform, so only align to the alignment of the 8-byte type on the platform. Remove the explicit alignment of struct statfs as it's redundant.
* alpha: Fix signal thunk unwind infoRichard Henderson2013-11-162-4/+19
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* rename configure.in to configure.acMike Frysinger2013-10-3050-25/+119
| | | | | | | Autoconf has been deprecating configure.in for quite a long time. Rename all our configure.in and preconfigure.in files to .ac. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Move entries to correct port ChangeLog files.Joseph Myers2013-10-183-11/+11
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* Fix typos.Yuri Chornoivan2013-10-123-2/+7
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* Fix typo in last changeAndreas Schwab2013-10-081-1/+1
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* m68k: use PIC for Scrt1.oAndreas Schwab2013-10-082-0/+25
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* Move powerpc ports pieces to libc.Joseph Myers2013-10-0462-13286/+31
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* e500 port: getcontext / setcontext / swapcontext.Joseph Myers2013-10-045-0/+161
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* ARM: Allow building __sigsetjmp as Thumb.Will Newton2013-10-042-3/+5
| | | | | | | | | | | Convert __sigsetjmp code to allow building as Thumb. ports/ChangeLog.arm: 2013-10-04 Will Newton <will.newton@linaro.org> * sysdeps/arm/setjmp.S (NO_THUMB): Remove define. (__sigsetjmp): Use Thumb supported instructions.
* ARM: Allow building __longjmp as Thumb.Will Newton2013-10-043-5/+10
| | | | | | | | | | | | | Convert __longjmp code to allow building as Thumb. ports/ChangeLog.arm: 2013-10-04 Will Newton <will.newton@linaro.org> * sysdeps/arm/__longjmp.S (NO_THUMB): Remove define. (__longjmp): Use Thumb supported instructions. * sysdeps/unix/sysv/linux/arm/____longjmp_chk.S (NO_THUMB): Remove define.
* fix changelog dateAlan Modra2013-10-041-1/+1
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* PowerPC floating point little-endian [1 of 15]Alan Modra2013-10-042-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | http://sourceware.org/ml/libc-alpha/2013-08/msg00081.html This is the first of a series of patches to ban ieee854_long_double and the ieee854_long_double macros when using IBM long double. union ieee854_long_double just isn't correct for IBM long double, especially when little-endian, and pretending it is OK has allowed a number of bugs to remain undetected in sysdeps/ieee754/ldbl-128ibm/. This changes the few places in generic code that use it. * stdio-common/printf_size.c (__printf_size): Don't use union ieee854_long_double in fpnum union. * stdio-common/printf_fphex.c (__printf_fphex): Likewise. Use signbit macro to retrieve sign from long double. * stdio-common/printf_fp.c (___printf_fp): Use signbit macro to retrieve sign from long double. * sysdeps/ieee754/ldbl-128ibm/printf_fphex.c: Adjust for fpnum change. * sysdeps/ieee754/ldbl-128/printf_fphex.c: Likewise. * sysdeps/ieee754/ldbl-96/printf_fphex.c: Likewise. * sysdeps/x86_64/fpu/printf_fphex.c: Likewise. * math/test-misc.c (main): Don't use union ieee854_long_double. ports/ * sysdeps/ia64/fpu/printf_fphex.c: Adjust for fpnum change.
* 2013-09-26 Steve Ellcey <sellcey@mips.com>Steve Ellcey2013-10-036-0/+6
| | | | | | | | | | [BZ #15632] * sysdeps/mips/mips32/fpu/e_sqrt.c: New. * sysdeps/mips/mips32/fpu/e_sqrtf.c: New. * sysdeps/mips/mips64/n32/fpu/e_sqrt.c: New. * sysdeps/mips/mips64/n32/fpu/e_sqrtf.c: New. * sysdeps/mips/mips64/n64/fpu/e_sqrt.c: New. * sysdeps/mips/mips64/n64/fpu/e_sqrtf.c: New.
* 2013-09-26 Steve Ellcey <sellcey@mips.com>Steve Ellcey2013-10-031-0/+10
| | | | | | | | | | [BZ #15632] * sysdeps/mips/mips32/fpu/e_sqrt.c: New. * sysdeps/mips/mips32/fpu/e_sqrtf.c: New. * sysdeps/mips/mips64/n32/fpu/e_sqrt.c: New. * sysdeps/mips/mips64/n32/fpu/e_sqrtf.c: New. * sysdeps/mips/mips64/n64/fpu/e_sqrt.c: New. * sysdeps/mips/mips64/n64/fpu/e_sqrtf.c: New.
* ARM: Add pointer encryption support.Will Newton2013-10-037-6/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for pointer encryption in glibc internal structures in C and assembler code. Pointer encryption is a glibc security feature described here: https://sourceware.org/glibc/wiki/PointerEncryption The ARM implementation uses global variables instead of thread pointer relative accesses to get the value of the pointer encryption guard because accessing the thread pointer can be very expensive on older ARM cores. ports/ChangeLog.arm: 2013-10-03 Will Newton <will.newton@linaro.org> * sysdeps/arm/__longjmp.S (__longjmp): Demangle fp, sp and lr when restoring register values. * sysdeps/arm/include/bits/setjmp.h (JMP_BUF_REGLIST): Remove sp and lr from list and replace fp with a4. * sysdeps/arm/jmpbuf-unwind.h (_jmpbuf_sp): New function. (_JMPBUF_UNWINDS_ADJ): Call _jmpbuf_sp. * sysdeps/arm/setjmp.S (__sigsetjmp): Mangle fp, sp and lr before storing register values. * sysdeps/arm/sysdep.h (LDST_GLOBAL): New macro. * sysdeps/unix/sysv/linux/arm/sysdep.h (PTR_MANGLE): New macro. (PTR_DEMANGLE): Likewise. (PTR_MANGLE2): Likewise. (PTR_DEMANGLE2): Likewise.
* alpha: Improve conditions under which PTR_MANGLE is definedRichard Henderson2013-10-012-31/+26
| | | | | After 0b1f8e35640f5b3f7af11764ade3ff060211c309, we now have a __pointer_chk_guard_local for the static libc.
* [AArch64] Fix BE access to errno.Andrew Pinski2013-09-302-1/+6
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* [AArch64] Support __mcount profiling.Marcus Shawcroft2013-09-242-8/+12
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* [AArch64] Adding sigcontextinfo.hMarcus Shawcroft2013-09-242-0/+39
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* ports/sysdeps/arm/nptl/tls.h: Remove TLS_INIT_TP_EXPENSIVE.Will Newton2013-09-242-4/+5
| | | | | | | | | | | This define was removed from the rest of the tree eight years ago. ports/ChangeLog.arm: 2013-09-24 Will Newton <will.newton@linaro.org> * ports/sysdeps/arm/nptl/tls.h (TLS_INIT_TP_EXPENSIVE): Remove macro.
* 2013-09-23 Steve Ellcey <sellcey@mips.com>Steve Ellcey2013-09-232-0/+131
| | | | | | | | | | | | | | | | | | | | | | | * sysdeps/mips/math_private.h (libc_feholdexcept_mips): New function. (libc_feholdexcept): New macro. (libc_feholdexceptf): New macro. (libc_feholdexceptl): New macro. (libc_fesetround_mips): New function. (libc_fesetround): New macro. (libc_fesetroundf): New macro. (libc_fesetroundl): New macro. (libc_feholdexcept_setround_mips): New function. (libc_feholdexcept_setround): New macro. (libc_feholdexcept_setroundf): New macro. (libc_feholdexcept_setroundl): New macro. (libc_fesetenv_mips): New function. (libc_fesetenv): New macro. (libc_fesetenvf): New macro. (libc_fesetenvl): New macro. (libc_feupdateenv_mips): New function. (libc_feupdateenv): New macro. (libc_feupdateenvf): New macro. (libc_feupdateenvl): New macro.
* MIPS: bits/atomic.h: Fix comment typoMaciej W. Rozycki2013-09-232-1/+5
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* 2013-09-23 Steve Ellcey <sellcey@mips.com>Steve Ellcey2013-09-233-3/+8
| | | | | * sysdeps/mips/fpu/fegetround.c (fegetround): Use _FPU_RC_MASK. * sysdeps/mips/fpu/fesetround.c (fesetround): Use _FPU_RC_MASK.
* 2013-09-19 Steve Ellcey <sellcey@mips.com>Steve Ellcey2013-09-232-0/+6
| | | | * sysdeps/mips/fpu_control.h (_FPU_RC_MASK): New.
* 2013-09-23 Steve Ellcey <sellcey@mips.com>Steve Ellcey2013-09-232-3/+8
| | | | | * sysdeps/mips/fpu_control.h (comments): Add capitalization and periods to match GNU standard.
* BZ #15754: CVE-2013-4788Carlos O'Donell2013-09-234-0/+19
| | | | | | | | | | | | The pointer guard used for pointer mangling was not initialized for static applications resulting in the security feature being disabled. The pointer guard is now correctly initialized to a random value for static applications. Existing static applications need to be recompiled to take advantage of the fix. The test tst-ptrguard1-static and tst-ptrguard1 add regression coverage to ensure the pointer guards are sufficiently random and initialized to a default value.
* Make __ffs hiddenAndreas Schwab2013-09-209-0/+22
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* Remove trailing space.Steve Ellcey2013-09-201-1/+1
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* 2013-09-20 Steve Ellcey <sellcey@mips.com>Steve Ellcey2013-09-201-90/+0
| | | | | * sysdeps/mips/memset.S: Change prefetching and add loop unrolling. * sysdeps/mips/mips64/memset.S: Remove.
* 2013-09-20 Steve Ellcey <sellcey@mips.com>Steve Ellcey2013-09-202-56/+343
| | | | | * sysdeps/mips/memset.S: Change prefetching and add loop unrolling. * sysdeps/mips/mips64/memset.S: Remove.
* Improve atomic locking for ARM.Maxim Kuvyrkov2013-09-192-8/+96
| | | | | | | | | | [BZ #15640] * sysdeps/arm/bits/atomic.h (atomic_exchange_acq, atomic_exchange_rel) (atomic_compare_and_exchange_bool_acq) (atomic_compare_and_exchange_val_acq) (atomic_compare_and_exchange_bool_rel) (atomic_compare_and_exchange_val_rel): Use __atomic_exchange_n and __atomic_compare_exchange_n builtins when GCC supports them.
* MIPS: IEEE 754-2008 NaN encoding supportMaciej W. Rozycki2013-09-1815-50/+640
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It has been a long practice for software using IEEE 754 floating-point arithmetic run on MIPS processors to use an encoding of Not-a-Number (NaN) data different to one used by software run on other processors. And as of IEEE 754-2008 revision [1] this encoding does not follow one recommended in the standard, as specified in section 6.2.1, where it is stated that quiet NaNs should have the first bit (d1) of their significand set to 1 while signalling NaNs should have that bit set to 0, but MIPS software interprets the two bits in the opposite manner. As from revision 3.50 [2][3] the MIPS Architecture provides for processors that support the IEEE 754-2008 preferred NaN encoding format. As the two formats (further referred to as "legacy NaN" and "2008 NaN") are incompatible to each other, tools have to provide support for the two formats to help people avoid using incompatible binary modules. The change is comprised of two functional groups of features, both of which are required for correct support. 1. Dynamic linker support. To enforce the NaN encoding requirement in dynamic linking a new ELF file header flag has been defined. This flag is set for 2008-NaN shared modules and executables and clear for legacy-NaN ones. The dynamic linker silently ignores any incompatible modules it encounters in dependency processing. To avoid unnecessary processing of incompatible modules in the presence of a shared module cache, a set of new cache flags has been defined to mark 2008-NaN modules for the three ABIs supported. Changes to sysdeps/unix/sysv/linux/mips/readelflib.c have been made following an earlier code quality suggestion made here: http://sourceware.org/ml/libc-ports/2009-03/msg00036.html and are therefore a little bit more extensive than the minimum required. Finally a new name has been defined for the dynamic linker so that 2008-NaN and legacy-NaN binaries can coexist on a single system that supports dual-mode operation and that a legacy dynamic linker that does not support verifying the 2008-NaN ELF file header flag is not chosen to interpret a 2008-NaN binary by accident. 2. Floating environment support. IEEE 754-2008 features are controlled in the Floating-Point Control and Status (FCSR) register and updates are needed to floating environment support so that the 2008-NaN flag is set correctly and the kernel default, inferred from the 2008-NaN ELF file header flag at the time an executable is loaded, respected. As the NaN encoding format is a property of GCC code generation that is both a user-selected GCC configuration default and can be overridden with GCC options, code that needs to know what NaN encoding standard it has been configured for checks for the __mips_nan2008 macro that is defined internally by GCC whenever the 2008-NaN mode has been selected. This mode is determined at the glibc configuration time and therefore a few consistency checks have been added to catch cases where compilation flags have been overridden by the user. The 2008 NaN set of features relies on kernel support as the in-kernel floating-point emulator needs to be aware of the NaN encoding used even on hard-float processors and configure the FPU context according to the value of the 2008 NaN ELF file header flag of the executable being started. As at this time work on kernel support is still in progress and the relevant changes have not made their way yet to linux.org master repository. Therefore the minimum version supported has been artificially set to 10.0.0 so that 2008-NaN code is not accidentally run on a Linux kernel that does not suppport it. It is anticipated that the version is adjusted later on to the actual initial linux.org kernel version to support this feature. Legacy NaN encoding support is unaffected, older kernel versions remain supported. [1] "IEEE Standard for Floating-Point Arithmetic", IEEE Computer Society, IEEE Std 754-2008, 29 August 2008 [2] "MIPS Architecture For Programmers, Volume I-A: Introduction to the MIPS32 Architecture", MIPS Technologies, Inc., Document Number: MD00082, Revision 3.50, September 20, 2012 [3] "MIPS Architecture For Programmers, Volume I-A: Introduction to the MIPS64 Architecture", MIPS Technologies, Inc., Document Number: MD00083, Revision 3.50, September 20, 2012
* ARM: Improve armv7 memcpy performance.Will Newton2013-09-162-6/+10
| | | | | | | | | | | | | | Only enter the aligned copy loop with buffers that can be 8-byte aligned. This improves performance slightly on Cortex-A9 and Cortex-A15 cores for large copies with buffers that are 4-byte aligned but not 8-byte aligned. ports/ChangeLog.arm: 2013-09-16 Will Newton <will.newton@linaro.org> * sysdeps/arm/armv7/multiarch/memcpy_impl.S: Tighten check on entry to aligned copy loop to improve performance.
* Add O_TMPFILE to <fcntl.h>Andreas Schwab2013-09-114-0/+11
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* Define MMAP2_PAGE_SHIFT to -1 for m68k.Joseph Myers2013-09-042-0/+9
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* hppa: add fanotify_markMike Frysinger2013-09-023-0/+11
| | | | | | | | | | | | | | | | | | | Another example of all the 64bit arches getting the definition via a common file, but the 32bit ones all adding it by themselves and hppa was missed. I'm not entirely sure about the usage of GLIBC_2.19 symbols here. We'd like to backport this so people can use it, but it means we'd be releasing a glibc-2.17/glibc-2.18 with a GLIBC_2.19 symbol in it. But maybe it won't be a big deal since you'd only get that 2.19 ref if you actually used the symbol ? There hasn't been a glibc release where hppa worked w/out a bunch of patches, so in reality there's only two distros that matter -- Gentoo and Debian. Reported-by: Jeroen Roovers <jer@gentoo.org> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Use sfi_* macros in armv6t2 strlen.Roland McGrath2013-08-302-9/+16
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* Make armv6t2 strlen work in ARM mode too.Roland McGrath2013-08-302-2/+30
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* Fix then/than typos.Ondřej Bílka2013-08-304-8/+16
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* Fix typos.Ondřej Bílka2013-08-3016-16/+41
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* ARM: Fix clone code when built for Thumb.Will Newton2013-08-302-2/+8
| | | | | | | | | | | | | The mov lr, pc instruction will lose the Thumb bit from the return address so use blx lr instead. ports/ChangeLog.arm: 2013-08-30 Will Newton <will.newton@linaro.org> [BZ #15909] * sysdeps/unix/sysv/linux/arm/clone.S (__clone): Use blx instead of mov lr, pc.
* sysdeps/arm/armv6t2/strlen.S: strlen implementation for armv6t2.Will Newton2013-08-302-0/+145
| | | | | | | | | | | This implementation of strlen is faster than the armv6 version for all string lengths greater than 1 on a Cortex-A15. ports/ChangeLog.arm: 2013-08-09 Will Newton <will.newton@linaro.org> * sysdeps/arm/armv6t2/strlen.S: New file.
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