about summary refs log tree commit diff
path: root/ports
Commit message (Collapse)AuthorAgeFilesLines
* m68k: update libm test ULPsAndreas Schwab2013-04-112-4/+3600
|
* New <math.h> macro named issignaling to check for a signaling NaN (sNaN).Thomas Schwinge2013-04-0217-0/+121
| | | | It is based on draft TS 18661 and currently enabled as a GNU extension.
* ARM: fix preconfigure.Mans Rullgard2013-03-263-2/+7
|
* Use LIBC_CONFIG_VAR for MIPS default-abi setting.Joseph Myers2013-03-214-5/+11
|
* Use LIBC_CONFIG_VAR for ARM default-abi setting.Joseph Myers2013-03-204-7/+14
|
* aarch64: Move rtld link to /libAndreas Schwab2013-03-193-0/+8
|
* ARM: Make dl-tlsdesc.S use sfi_breg, respect ARM_ALWAYS_BX and ↵Roland McGrath2013-03-183-9/+38
| | | | ARM_NO_INDEX_REGISTER.
* Better distinguish between NaN/qNaN/sNaN.Thomas Schwinge2013-03-151-8/+8
|
* Avoid duplicate MAP_ANONYMOUS definition for MIPS GNU/Linux.Thomas Schwinge2013-03-152-1/+5
| | | | Follow-up to commit 664a9ce4ca40feabff781fff044c93a43ae15b59.
* ARM: sfi_sp assembler macroRoland McGrath2013-03-153-1/+9
|
* ARM: sfi_breg assembler macroRoland McGrath2013-03-1518-189/+404
|
* aarch64: use lib64 as default lib and slib directoryAndreas Schwab2013-03-143-0/+31
|
* ARM_BX_ALIGN_LOG2Roland McGrath2013-03-134-12/+63
|
* ARM: Handle ARM_ALWAYS_BX in {add,sub}_n.S code.Roland McGrath2013-03-132-0/+9
|
* ARM: Support avoiding pc as destination register.Roland McGrath2013-03-134-2/+67
|
* ARM: Make armv6t2 memchr implementation usable without Thumb.Roland McGrath2013-03-122-2/+26
|
* ARM: Change register allocation in armv6t2 memchr implementation.Roland McGrath2013-03-122-15/+20
|
* ia64: fix set-but-unused warnings with syscallsMike Frysinger2013-03-122-2/+11
| | | | | | | | | | | These macros often set up a variable that later macros sometimes do not use. Add unused attribute to avoid that. Similarly, the ia64 code tends to check the err field rather than the val (which is opposite of most arches) leading to the same kind of warning. Replace this with a dummy reference. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* ia64: fix strict aliasing warnings with libm errorMike Frysinger2013-03-122-58/+81
| | | | | | | | The current code declares double constants by using a char buffer and then casting the pointer to a different type. This makes the aliasing logic unhappy. Change it to use a union instead to avoid that. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* ia64: fix strict aliasing warnings with func descriptorsMike Frysinger2013-03-125-13/+34
| | | | | | | | | | | Function pointers on ia64 are like parisc -- they're plabels. While the parisc port enjoys a gcc builtin for extracting the address here, ia64 has no such luck. Casting & dereferencing in one go triggers a strict aliasing warning. Use a union to fix that. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Add comments about ARM configure -fno-unwind-tables handling.Joseph Myers2013-03-115-0/+21
|
* ARM: Consolidate setjmp details in include/bits/setjmp.h file.Roland McGrath2013-03-116-10/+28
|
* ARM: Convert string/ assembly to unified syntax.Roland McGrath2013-03-115-40/+53
|
* ARM: Use r10 instead of r9.Roland McGrath2013-03-113-18/+21
|
* AM33: Use <bits/mman.h>Andreas Jaeger2013-03-112-61/+7
|
* Use <bits/mman.h> on ia64Andreas Jaeger2013-03-112-74/+7
|
* Clean up ARM preconfigure.Roland McGrath2013-03-113-46/+109
|
* Remove extra pthread_atfork compat symbolsAndreas Schwab2013-03-1110-6/+28
|
* ia64: makecontext: fix signed warningsMike Frysinger2013-03-102-2/+7
| | | | | | | | The ia64_rse_is_rnat_slot func expects an unsigned pointer, but we're passing in a signed pointer. The signness doesn't matter here, so convert it to unsigned. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* ia64: fix NEED_DL_SYSINFO_DSO conditionalsMike Frysinger2013-03-102-23/+13
| | | | | | | The recent change to clean up these defines missed the ia64 logic. Update it accordingly. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* arm: Implement armv6 optimized string routinesRichard Henderson2013-03-078-0/+707
| | | | | | | | The strcpy and strchr (and related) functions are four times faster than the byte-by-byte default versions. The strlen function is twice as fast for long strings and 50% faster for short strings over the armv4 version.
* AARCH64: Use <bits/mman-linux.h>Andreas Jaeger2013-03-072-73/+8
| | | | | * sysdeps/unix/sysv/linux/aarch64/bits/mman.h: Remove all defines provided by bits/mman-linux.h and include <bits/mman-linux.h>.
* Use <bits/mman-linux.h> for MIPSAndreas Jaeger2013-03-062-72/+9
| | | | | | | | | * sysdeps/unix/sysv/linux/bits/mman-linux.h (MAP_ANONYMOUS): Allow definition via __MAP_ANONYMOUS. * sysdeps/unix/sysv/linux/mips/bits/mman.h: Remove all defines provided by bits/mman-linux.h and include <bits/mman-linux.h>. (__MAP_ANONYMOUS): Define.
* arm: Add optimized add_n and sub_nRichard Henderson2013-03-063-0/+88
| | | | | | | | Written from scratch rather than copied from GMP, due to LGPL 2.1 vs GPL 3, but tested with the GMP testsuite. This is 250% faster than the generic code as measured on Cortex-A15, and the same speed as GMP on the same core, and probably everywhere.
* arm: Add optimized submul_1Richard Henderson2013-03-062-0/+69
| | | | | | | | Written from scratch rather than copied from GMP, due to LGPL 2.1 vs GPL 3, but tested with the GMP testsuite. This is 50% faster than the generic code as measured on Cortex-A15. It is 25% slower than the current GMP routine on the same core.
* arm: Add optimized addmul_1Richard Henderson2013-03-062-0/+68
| | | | | | | | | Written from scratch rather than copied from GMP, due to LGPL 2.1 vs GPL 3, but tested with the GMP testsuite. This is 25% faster than the generic code as measured on Cortex-A15, and the same speed as GMP on the same core. It's probably slower than GMP on the A8 and A9 cores though.
* arm: Add optimized ffs for armv6t2Richard Henderson2013-03-063-0/+88
|
* arm: Implement hard-tp for GET_TLSRichard Henderson2013-03-064-11/+30
|
* arm: Tidy architecture selectionRichard Henderson2013-03-063-8/+45
|
* arm: Unless arm4t, pop return address directly into pcRichard Henderson2013-03-063-5/+14
|
* arm: Commonize BX conditionalsRichard Henderson2013-03-064-30/+21
| | | | Add BLX macro in addition and use it where appropriate.
* arm: Delete LOADREGS macroRichard Henderson2013-03-063-5/+4
| | | | | | There was only one user. It's "condition" argument was used for "ia" rather than an actual condition. The apcs26 syntax is almost certainly not needed, given current binutils requirements.
* arm: Use push/pop mnemonicsRichard Henderson2013-03-0620-134/+154
| | | | | | For arm this makes no difference--the result is bit-for-bit identical; for thumb this results in smaller encodings. Perhaps it ought not and this is in fact an assembler bug, but I also think it's clearer.
* arm: Enable thumb2 mode in assembly filesRichard Henderson2013-03-062-2/+14
| | | | | | The preceeding patches have allowed for the few incompatibilities between arm and thumb2 mode, or have marked the file as not wanting to use thumb2 mode.
* arm: Introduce and use GET_TLSRichard Henderson2013-03-0610-42/+77
| | | | | | Factor out the sequence needed to call kuser_get_tls, as we can't play subtract into pc games in thumb mode. Prepare for hard-tp, pulling the save of LR into the macro.
* arm: Introduce and use NEGOFF series of macrosRichard Henderson2013-03-066-14/+43
| | | | | | | | | There are several places in which we access negative offsets from the thread-pointer, but thumb2 only supports positive offsets in memory references. Avoid duplicating the rather large macros in which these references are embedded by abstracting out the operation.
* arm: Introduce and use LDST_PCRELRichard Henderson2013-03-065-24/+47
| | | | | Macro-ising the few instances where we need to distinguish between arm and thumb pc-relative memory operations.
* Sync with Linux 3.8Andreas Jaeger2013-03-0611-2/+35
|
* Update date of last entryAndreas Jaeger2013-03-061-1/+1
|
* Use <bits/mman-linux.h> on M68kAndreas Jaeger2013-03-062-74/+7
|
generated by cgit-pink 1.4.1 (git 2.36.1) at 2024-11-20 17:34:04 +0000