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* Function name typo error in non-PIC case, fixed in this patch.Chung-Lin Tang2015-02-052-1/+6
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* Fix two bugs in sparc atomics.David S. Miller2015-01-312-7/+14
| | | | | | | | * sysdeps/sparc/sparc32/bits/atomic.h (__sparc32_atomic_do_unlock24): Put the memory barrier before the unlock not after it. (__v9_compare_and_exchange_val_32_acq): Use unions to avoid getting volatile register usage warnings from the compiler.
* Fix sparc semaphore implementation after recent changes.David S. Miller2015-01-3118-703/+692
| | | | | | | | | | | | | | | | | | | | | | | | * sysdeps/sparc/nptl/sem_init.c: Delete. * sysdeps/sparc/nptl/sem_post.c: Delete. * sysdeps/sparc/nptl/sem_timedwait.c: Delete. * sysdeps/sparc/nptl/sem_wait.c: Delete. * sysdeps/sparc/sparc32/sem_init.c: New file. * sysdeps/sparc/sparc32/sem_waitcommon.c: New file. * sysdeps/sparc/sparc32/sem_open.c: Generic nptl version with padding explicitly initialized. * sysdeps/sparc/sparc32/sem_post.c: Generic nptl version using padding for in-semaphore spinlock. * sysdeps/sparc/sparc32/sem_wait.c: Likewise. * sysdeps/sparc/sparc32/sem_trywait.c: Delete. * sysdeps/sparc/sparc32/sem_timedwait.c: Delete. * sysdeps/sparc/sparc32/sparcv9/sem_init.c: New file. * sysdeps/sparc/sparc32/sparcv9/sem_open.c: New file. * sysdeps/sparc/sparc32/sparcv9/sem_post.c: New file. * sysdeps/sparc/sparc32/sparcv9/sem_waitcommon.c: New file. * sysdeps/sparc/sparc32/sparcv9/sem_wait.c: Redirect to nptl version. * sysdeps/sparc/sparc32/sparcv9/sem_timedwait.c: Delete. * sysdeps/sparc/sparc32/sparcv9/sem_trywait.c: Delete.
* Use AVX unaligned memcpy only if AVX2 is availableH.J. Lu2015-01-3010-10/+37
| | | | | | | | | | | | | | | | | | | | | | memcpy with unaligned 256-bit AVX register loads/stores are slow on older processorsl like Sandy Bridge. This patch adds bit_AVX_Fast_Unaligned_Load and sets it only when AVX2 is available. [BZ #17801] * sysdeps/x86_64/multiarch/init-arch.c (__init_cpu_features): Set the bit_AVX_Fast_Unaligned_Load bit for AVX2. * sysdeps/x86_64/multiarch/init-arch.h (bit_AVX_Fast_Unaligned_Load): New. (index_AVX_Fast_Unaligned_Load): Likewise. (HAS_AVX_FAST_UNALIGNED_LOAD): Likewise. * sysdeps/x86_64/multiarch/memcpy.S (__new_memcpy): Check the bit_AVX_Fast_Unaligned_Load bit instead of the bit_AVX_Usable bit. * sysdeps/x86_64/multiarch/memcpy_chk.S (__memcpy_chk): Likewise. * sysdeps/x86_64/multiarch/mempcpy.S (__mempcpy): Likewise. * sysdeps/x86_64/multiarch/mempcpy_chk.S (__mempcpy_chk): Likewise. * sysdeps/x86_64/multiarch/memmove.c (__libc_memmove): Replace HAS_AVX with HAS_AVX_FAST_UNALIGNED_LOAD. * sysdeps/x86_64/multiarch/memmove_chk.c (__memmove_chk): Likewise.
* Include <signal.h> in sysdeps/nptl/allocrtsig.cAndreas Schwab2015-01-292-0/+5
| | | | | Architectures which don't use hp-timing-common.h don't include <signal.h> via <sys/param.h>.
* Fix up ChangeLog formattingSiddhesh Poyarekar2015-01-291-12/+12
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* Initialize nscd stats data [BZ #17892]Siddhesh Poyarekar2015-01-293-1/+8
| | | | | | | | | | | | | | | | | | | | | | | The padding bytes in the statsdata struct are not initialized, due to which valgrind throws a warning: ==11384== Memcheck, a memory error detector ==11384== Copyright (C) 2002-2012, and GNU GPL'd, by Julian Seward et al. ==11384== Using Valgrind-3.8.1 and LibVEX; rerun with -h for copyright info ==11384== Command: nscd -d ==11384== Fri 25 Apr 2014 10:34:53 AM CEST - 11384: handle_request: request received (Version = 2) from PID 11396 Fri 25 Apr 2014 10:34:53 AM CEST - 11384: GETSTAT ==11384== Thread 6: ==11384== Syscall param socketcall.sendto(msg) points to uninitialised byte(s) ==11384== at 0x4E4ACDC: send (in /lib64/libpthread-2.12.so) ==11384== by 0x11AF6B: send_stats (in /usr/sbin/nscd) ==11384== by 0x112F75: nscd_run_worker (in /usr/sbin/nscd) ==11384== by 0x4E439D0: start_thread (in /lib64/libpthread-2.12.so) ==11384== by 0x599AB6C: clone (in /lib64/libc-2.12.so) ==11384== Address 0x15708395 is on thread 6's stack Fix the warning by initializing the structure.
* Clarify math/README.libm-test. Add "How to read the test output."Martin Sebor2015-01-282-14/+71
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* tilegx32: set __HAVE_64B_ATOMICS to 0Chris Metcalf2015-01-282-1/+14
| | | | | | This is because of alignment issues in the sem_t support. tilegx32 does in fact support 64-bit atomics and we will need to revisit this after the 2.21 freeze.
* Disable 64-bit atomics for MIPS n32.Joseph Myers2015-01-282-1/+6
| | | | | | | | | | | | | | | | | | This patch disables use of 64-bit atomics for MIPS n32 to fix the problems with unaligned semaphores. Before 64-bit atomics are used for anything for which such alignment issues do not arise, and before the addition of any new ILP32 ports with 64-bit semaphores for which the ABI can be set to have the greater alignment (AARCH64?), a better approach will need to be established that allows architectures to declare their 64-bit atomics availability accurately, without doing so causing inappropriate use of such atomics on unaligned semaphores. Tested for MIPS n32 that this fixes the nptl/tst-sem3 failure. * sysdeps/mips/bits/atomic.h [_MIPS_SIM == _ABIN32] (__HAVE_64B_ATOMICS): Define to 0.
* powerpc: Fix fesetexceptflag [BZ#17885]Adhemerval Zanella2015-01-283-2/+6
| | | | | | | | | This patch fixes a bug introduced by 18f2945ae9216cfc, where it optimizes the FPSCR set by just issuing a mtfs instruction if new flag is different from older one. The issue is a typo, where the new flag should the the new value, instead of the old one. It fixes BZ#17885.
* powerpc: Fix fsqrt build in libm [BZ#16576]Adhemerval Zanella2015-01-287-111/+50
| | | | | | | | | | Some powerpc64 processors (e5500 core for instance) does not provide the fsqrt instruction, however current check to use in math_private.h is __WORDSIZE and _ARCH_PWR4 (ISA 2.02). This is patch change it to use the compiler flag _ARCH_PPCSQ (which is the same condition GCC uses to decide whether to generate fsqrt instruction). It fixes BZ#16576.
* iconv: Suppress array out of bounds warning.Andreas Krebbel2015-01-272-1/+12
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* ia64: avoid set-but-not-used warningAndreas Schwab2015-01-252-0/+8
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* m68k/coldfire: avoid warning about volatile register variablesAndreas Schwab2015-01-252-10/+13
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* m68k: fix missing definition of __feraiseexceptAndreas Schwab2015-01-252-0/+4
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* m68k: force inlining bswap functionsAndreas Schwab2015-01-252-4/+9
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* Fix segmentation fault when LD_LIBRARY_PATH contains only non-existings pathsBram2015-01-253-12/+18
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* powerpc: Fix powerpc64 build failure with binutils 2.22Adhemerval Zanella2015-01-243-2/+9
| | | | | | | | | | | | | | GLIBC memset optimization for POWER8 uses the '.machine power8' directive, which is only supported officially on binutils 2.24+. This causes a build failure on older binutils. Since the requirement of .machine power8 is to correctly assembly the 'mtvsrd' instruction and it is already handled by the MTVSRD_V1_R4 macro, there is no really needed of using it. The patch replaces the power8 with power7 for .machine directive. It fixes BZ#17869.
* powerpc: Fix ifuncmain6pie failure with GCC 4.9Adhemerval Zanella2015-01-243-2/+10
| | | | | | | | | | | This patch fix the elf/ifuncmain6pie failure when building with GCC 4.9+. For some reason, the compiler removes the branch taken code at resolve_ifunc (sysdeps/powerpc/powerpc64/dl-machine.h) as dead-code and thus the testcase fails because the ifunc resolves branches to an invalid memory location. It fixes by explicit adding a dependency of value based on odp variable to avoid compiler optimization. It fixes BZ#17868.
* Also treat model numbers 0x5a/0x5d as SilvermontH.J. Lu2015-01-232-1/+4
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* Treat model numbers 0x4a/0x4d as SilvermontH.J. Lu2015-01-232-0/+7
| | | | | * sysdeps/x86_64/multiarch/init-arch.c (__init_cpu_features): Treat model numbers 0x4a/0x4d as Intel Silvermont architecture.
* Also use uint64_t in __new_sem_wait_fastH.J. Lu2015-01-232-1/+2
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* Use uint64_t and (uint64_t) 1 for 64-bit intH.J. Lu2015-01-235-8/+20
| | | | | | | | | | | | | | | This patch replaces unsigned long int and 1UL with uint64_t and (uint64_t) 1 to support ILP32 targets like x32. [BZ #17870] * nptl/sem_post.c (__new_sem_post): Replace unsigned long int with uint64_t. * nptl/sem_waitcommon.c (__sem_wait_cleanup): Replace 1UL with (uint64_t) 1. (__new_sem_wait_slow): Replace unsigned long int with uint64_t. Replace 1UL with (uint64_t) 1. * sysdeps/nptl/internaltypes.h (new_sem): Replace unsigned long int with uint64_t.
* Add missing libc_hidden_weak to stub if_nameindex, if_freenameindex.Roland McGrath2015-01-232-0/+5
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* Add missing libc_hidden_def to stub getrlimit64.Roland McGrath2015-01-232-0/+5
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* soft-fp: Use __label__ for all labels within macros.Joseph Myers2015-01-222-0/+13
| | | | | | | | | | | | | | | | | | | soft-fp has various macros containing labels and goto statements. Because label names are function-scoped, this is problematic for using the same macro more than once within a function, which some architectures do in the Linux kernel (the soft-fp version there predates the addition of any of these labels and gotos). This patch fixes this by using __label__ to make the labels local to the block with the __label__ declaration. Tested for powerpc-nofpu that installed stripped shared libraries are unchanged by this patch. * soft-fp/op-common.h (_FP_ADD_INTERNAL): Declare labels with __label__. (_FP_FMA): Likewise. (_FP_TO_INT_ROUND): Likewise. (_FP_FROM_INT): Likewise.
* BZ #16418: Fix powerpc get_clockfreq racinessAdhemerval Zanella2015-01-213-78/+74
| | | | | | | | This patch fix powerpc __get_clockfreq racy and cancel-safe issues by dropping internal static cache and by using nocancel file operations. The vDSO failure check is also removed, since kernel code does not return an error (it cleans cr0.so bit on function return) and the static code (to read value /proc) now uses non-cancellable calls.
* Update copyright year to 2015 for new files.Carlos O'Donell2015-01-213-3/+6
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* tst-getpw: Rewrite.Carlos O'Donell2015-01-212-6/+79
| | | | | | | | | | | The test is rewritten to look for the testable conditions and exit once they are all detected. This prevents the test from iterating over 2000 UIDs and looking up each one. It speeds up the test and prevents it from failing if the system under test has an NSS-based passwd that is slower than the test timeout. See: https://sourceware.org/ml/libc-alpha/2015-01/msg00394.html
* Fix tst_wcscpy.c test.Marek Polacek2015-01-212-1/+5
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* Fix recursive dlopen.Carlos O'Donell2015-01-2110-21/+222
| | | | | | | | | | | | | | | | | | | The ability to recursively call dlopen is useful for malloc implementations that wish to load other dynamic modules that implement reentrant/AS-safe functions to use in their own implementation. Given that a user malloc implementation may be called by an ongoing dlopen to allocate memory the user malloc implementation interrupts dlopen and if it calls dlopen again that's a reentrant call. This patch fixes the issues with the ld.so.cache mapping and the _r_debug assertion which prevent this from working as expected. See: https://sourceware.org/ml/libc-alpha/2014-12/msg00446.html
* Fix semaphore destruction (bug 12674).Carlos O'Donell2015-01-2134-2103/+732
| | | | | | | | | | | | | This commit fixes semaphore destruction by either using 64b atomic operations (where available), or by using two separate fields when only 32b atomic operations are available. In the latter case, we keep a conservative estimate of whether there are any waiting threads in one bit of the field that counts the number of available tokens, thus allowing sem_post to atomically both add a token and determine whether it needs to call futex_wake. See: https://sourceware.org/ml/libc-alpha/2014-12/msg00155.html
* Regenerate INSTALL.Carlos O'Donell2015-01-202-231/+230
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* Update libc.pot:Carlos O'Donell2015-01-202-238/+242
| | | | | | In preparation for providing a tarball to the translation project. * po/libc.pot: Regenerated.
* Commit nios2 port to master.Chung-Lin Tang2015-01-1798-0/+7681
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* S390: Get rid of linknamespace failures for utmp functions.Stefan Liebler2015-01-169-15/+62
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* S390: Get rid of linknamespace failures for string functions.Stefan Liebler2015-01-1616-80/+142
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* Fix powerpc-nofpu fesetenv namespace (bug 17748).Joseph Myers2015-01-142-1/+7
| | | | | | | | | | | | | When fixing namespace issues for <fenv.h> functions I missed one call to fesetenv for powerpc-nofpu. This patch changes this to a call to __fesetenv. Tested for powerpc-nofpu; it fixes the previously observed math.h linknamespace test failures. [BZ #17748] * sysdeps/powerpc/nofpu/feholdexcpt.c (__feholdexcept): Call __fesetenv instead of fesetenv.
* [s390] Define a __tls_get_addr macro to avoid declaring it againSiddhesh Poyarekar2015-01-142-0/+12
| | | | | | | | | | | | | | commit 050f7298e1ecc39887c329037575ccd972071255 added an extern declaration for __tls_get_addr that conflicts with the one in s390 dl-tls.h, based on whether __tls_get_addr is defined as a macro. The rationale seems to be based on the assumption that __tls_get_addr is exported for every architecture and hence an internal non-plt alias is needed. This is not true for s390 though, since it exports __tls_get_offset and not __tls_get_addr. This results in tst-audit9 being stuck in an infinite loop. This patch fixes this by defining a __tls_get_addr macro to itself so as to not use the conflicting declaration.
* powerpc: Fix POWER7/PPC64 performance regression on LEAdhemerval Zanella2015-01-132-588/+285
| | | | | | | | | | | | | | | | | This patch fixes a performance regression on the POWER7/PPC64 memcmp porting for Little Endian. The LE code uses 'ldbrx' instruction to read the memory on byte reversed form, however ISA 2.06 just provide the indexed form which uses a register value as additional index, instead of a fixed value enconded in the instruction. And the port strategy for LE uses r0 index value and update the address value on each compare loop interation. For large compare size values, it adds 8 more instructions plus some more depending of trailing size. This patch fixes it by adding pre-calculate indexes to remove the address update on loops and tailing sizes. For large sizes it shows a considerable gain, with double performance pairing with BE.
* powerpc: Optimized strncmp for POWER8/PPC64Adhemerval Zanella2015-01-137-7/+387
| | | | | | | | | | This patch adds an optimized POWER8 strncmp. The implementation focus on speeding up unaligned cases follwing the ideas of power8 strcmp. The algorithm first check the initial 16 bytes, then align the first function source and uses unaligned loads on second argument only. Aditional checks for page boundaries are done for unaligned cases (where sources alignment are different).
* powerpc: Optimize POWER7 strcmp trailing checksRajalakshmi Srinivasaraghavan2015-01-132-114/+89
| | | | | | This patch optimized the POWER7 trailing check by avoiding using byte read operations and instead use the doubleword already readed with bitwise operations.
* Fix scanf15.c testsuite build on sparc.David S. Miller2015-01-132-0/+6
| | | | * include/signal.h (__sigreturn): Guard with __USE_MISC.
* Remove some references to bcopy/bcmp/bzero.Roland McGrath2015-01-136-11/+16
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* powerpc: Optimized strcmp for POWER8/PPC64Adhemerval Zanella2015-01-137-4/+318
| | | | | | | This patch adds an optimized POWER8 strcmp using unaligned accesses. The algorithm first check the initial 16 bytes, then align the first function source and uses unaligned loads on second argument only. Aditional checks for page boundaries are done for unaligned cases
* powerpc: Optimized st{r,p}ncpy for POWER8/PPC64Adhemerval Zanella2015-01-1310-7/+559
| | | | | | | | | | | | | This patch adds an optimized POWER8 st{r,p}ncpy using unaligned accesses. It shows 10%-80% improvement over the optimized POWER7 one that uses only aligned accesses, specially on unaligned inputs. The algorithm first read and check 16 bytes (if inputs do not cross a 4K page size). The it realign source to 16-bytes and issue a 16 bytes read and compare loop to speedup null byte checks for large strings. Also, different from POWER7 optimization, the null pad is done inline in the implementation using possible unaligned accesses, instead of realying on a memset call. Special case is added for page cross reads.
* powerpc: Optimized strncat for POWER7/PPC64Adhemerval Zanella2015-01-134-270/+35
| | | | | | | | | | | With 3eb38795dbbbd816 (Simplify strncat) the generic algorithms uses strlen, strnlen, and memcpy. This is faster than POWER7 current implementation, especially for unaligned strings (where POWER7 code uses byte-byte operations). This patch removes the assembly implementation and uses a multiarch specialization based on default algorithm calling optimized POWER7 symbols.
* powerpc: Optimized strcat for POWER8/PPC64Adhemerval Zanella2015-01-135-4/+49
| | | | | With new optimized strcpy for POWER8, this patch adds an optimized strcat which uses it along with default implementation at strings/.
* powerpc: Optimized st{r,p}cpy for POWER8/PPC64Adhemerval Zanella2015-01-139-3/+398
| | | | | | | | | | | | This patch adds an optimized POWER8 strcpy using unaligned accesses. For strings up to 16 bytes the implementation first calculate the string size, like strlen, and issues a memcpy. For larger strings, source is first aligned to 16 bytes and then tested over a loop that reads 16 bytes am combine the cmpb results for speedup. Special case is added for page cross reads. It shows 30%-60% improvement over the optimized POWER7 one that uses only aligned accesses.
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