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* CVE-2013-2207, BZ #15755: Disable pt_chown.Carlos O'Donell2013-07-2111-7/+100
| | | | | | | | | | | | | | | | | | | | | | | The helper binary pt_chown tricked into granting access to another user's pseudo-terminal. Pre-conditions for the attack: * Attacker with local user account * Kernel with FUSE support * "user_allow_other" in /etc/fuse.conf * Victim with allocated slave in /dev/pts Using the setuid installed pt_chown and a weak check on whether a file descriptor is a tty, an attacker could fake a pty check using FUSE and trick pt_chown to grant ownership of a pty descriptor that the current user does not own. It cannot access /dev/pts/ptmx however. In most modern distributions pt_chown is not needed because devpts is enabled by default. The fix for this CVE is to disable building and using pt_chown by default. We still provide a configure option to enable hte use of pt_chown but distributions do so at their own risk.
* Update Sparc ULPs.David S. Miller2013-07-202-0/+10
| | | | | * sysdeps/sparc/fpu/libm-test-ulps: Update ULPs to handle minor difference between 32-bit and 64-bit.
* m68k: use _dl_static_init to set GLR0(dl_pagesize)Andreas Schwab2013-07-215-2/+134
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* tile: add missing semicolon in <bits/ptrace.h>Chris Metcalf2013-07-192-1/+6
| | | | | | Change 521c6785e1fc94d added the enum but missed the semicolon. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
* Clean up whitespace in lock elision patches.Dominik Vogt2013-07-1915-31/+52
| | | | Signed-off-by: Carlos O'Donell <carlos@redhat.com>
* Remove remains of rwlock elision which is not implemented yet.Dominik Vogt2013-07-193-11/+8
| | | | | | | | | | | | | | | Signed-off-by: Carlos O'Donell <carlos@redhat.com> --- nptl/ 2013-07-19 Dominik Vogt <vogt@de.ibm.com> * sysdeps/unix/sysv/linux/x86/elision-conf.c: Remove __rwlock_rtm_enabled and __rwlock_rtm_read_retries. (elision_init): Don't set __rwlock_rtm_enabled. * sysdeps/unix/sysv/linux/x86/elision-conf.h: Remove __rwlock_rtm_enabled.
* BZ #15711: Avoid circular dependency for syscall.hCarlos O'Donell2013-07-163-3/+17
| | | | | | | | | | | | | | | | | | The generated header is compiled with `-ffreestanding' to avoid any circular dependencies against the installed implementation headers. Such a dependency would require the implementation header to be installed before the generated header could be built (See bug 15711). In current practice the generated header dependencies do not include any of the implementation headers removed by the use of `-ffreestanding'. --- 2013-07-15 Carlos O'Donell <carlos@redhat.com> [BZ #15711] * sysdeps/unix/sysv/linux/Makefile ($(objpfx)bits/syscall%h): Avoid system header dependency with -ffreestanding. ($(objpfx)bits/syscall%d): Likewise.
* Annotate more cases of math bug 15319.David S. Miller2013-07-132-16/+26
| | | | | | * math/libm-test.inc (casin_test_data): Annotate more cases of missing underflows from atanl/atan2l due to bug 15319. (casinh_test_data): Likewise.
* [AArch64] Adding -funwind-tables to backtrace.cMarcus Shawcroft2013-07-122-0/+8
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* [AArch64] Use _dl_static_init to set GLR0(dl_pagesize)Marcus Shawcroft2013-07-095-0/+136
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* Full from-scratch rebuild of sparc ULPs.David S. Miller2013-07-072-238/+77
| | | | * sysdeps/sparc/fpu/libm-test-ulps: Regenerate from scratch.
* tile: use _dl_static_init to set GLRO(gl_pagesize)Chris Metcalf2013-07-075-0/+134
| | | | | | A recently-added test (dlfcn/tststatic5) pointed out that tile was not properly initializing the variable pagesize in certain cases. This change just copies the existing code from MIPS.
* tile: update libm-test-ulps from scratchChris Metcalf2013-07-072-129/+2797
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* tile: use soft-fp for fma() and fmaf()Chris Metcalf2013-07-074-8/+105
| | | | | | The sfp-machine.h is based on the gcc version, but extended with required new macros by comparison with other architectures and by investigating the hardware support for FP on tile.
* Update x86 and x86_64 ulps on AMD FX-8350 with GCC 4.8.1.Jeroen Albers2013-07-053-16/+528
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* [AArch64] Regenerate libm-test-ulpsMarcus Shawcroft2013-07-052-0/+50
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* Fix lock elision help text in INSTALL and configureSiddhesh Poyarekar2013-07-044-4/+9
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* Update powerpc-fpu ULPs.Adhemerval Zanella2013-07-042-22/+150
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* Sync sys/ptrace with Linux 3.10Andreas Jaeger2013-07-0411-8/+193
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* Condition sysdeps/arm/include/bits/setjmp.h contents on _ISOMAC.Joseph Myers2013-07-032-2/+10
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* Regenerate powerpc-nofpu ULPs.Joseph Myers2013-07-032-183/+4158
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* Add x86 init-arch to nptlH.J. Lu2013-07-033-0/+7
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* Update i386 ULPs.Allan McRae2013-07-032-0/+84
| | | | * sysdeps/i386/fpu/libm-test-ulps: Update.
* Update sparc ULPs.David S. Miller2013-07-022-0/+50
| | | | * sysdeps/sparc/fpu/libm-test-ulps: Update.
* m68k: update libm test ULPsAndreas Schwab2013-07-032-6/+708
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* Update x86_64 ULPs.Markus Trippelsdorf2013-07-022-2/+322
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* Regenerate MIPS ulps.Joseph Myers2013-07-023-378/+9206
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* Regenerate ARM ulps.Joseph Myers2013-07-022-103/+2806
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* Regenerate x86 and x86_64 ulps.Joseph Myers2013-07-023-1593/+134
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* Make soft-float ARM use soft-fp fma/fmaf.Joseph Myers2013-07-025-0/+69
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* alpha: Update libm-test-ulps from scratchRichard Henderson2013-07-022-205/+70
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* Add lock elision to NEWS fileAndi Kleen2013-07-021-0/+6
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* Add a configure option to enable lock elision and disable by defaultAndi Kleen2013-07-028-0/+50
| | | | Can be enabled with --enable-lock-elision=yes at configure time.
* Disable elision for any pthread_mutexattr_settype callAndi Kleen2013-07-022-0/+10
| | | | | | | | | | PTHREAD_MUTEX_NORMAL requires deadlock for nesting, DEFAULT does not. Since glibc uses the same value (0) disable elision for any call to pthread_mutexattr_settype() with a 0 value. This implies that a program can disable elision by doing pthread_mutexattr_settype(&attr, PTHREAD_MUTEX_NORMAL) Based on a original proposal by Rich Felker.
* Add elision to pthread_mutex_{try,timed,un}lockAndi Kleen2013-07-0214-24/+267
| | | | | | | | | | | | | | | | | | | | | | | Add elision paths to the basic mutex locks. The normal path has a check for RTM and upgrades the lock to RTM when available. Trylocks cannot automatically upgrade, so they check for elision every time. We use a 4 byte value in the mutex to store the lock elision adaptation state. This is separate from the adaptive spin state and uses a separate field. Condition variables currently do not support elision. Recursive mutexes and condition variables may be supported at some point, but are not in the current implementation. Also "trylock" will not automatically enable elision unless some other lock call has been already called on the lock. This version does not use IFUNC, so it means every lock has one additional check for elision. Benchmarking showed the overhead to be negligible.
* Add minimal test suite changes for elision enabled kernelsAndi Kleen2013-07-023-1/+28
| | | | | | tst-mutex5 and 8 test some behaviour not required by POSIX, that elision changes. This changes these tests to not check this when elision is enabled at configure time.
* Add new internal mutex type flags for elision.Andi Kleen2013-07-023-9/+43
| | | | | | | | | | Add Enable/disable flags used internally Extend the mutex initializers to have the fields needed for elision. The layout stays the same, and this is not visible to programs. These changes are not exposed outside pthread
* Add the low level infrastructure for pthreads lock elision with TSXAndi Kleen2013-07-0212-0/+502
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Lock elision using TSX is a technique to optimize lock scaling It allows to run locks in parallel using hardware support for a transactional execution mode in 4th generation Intel Core CPUs. See http://www.intel.com/software/tsx for more Information. This patch implements a simple adaptive lock elision algorithm based on RTM. It enables elision for the pthread mutexes and rwlocks. The algorithm keeps track whether a mutex successfully elides or not, and stops eliding for some time when it is not. When the CPU supports RTM the elision path is automatically tried, otherwise any elision is disabled. The adaptation algorithm and its tuning is currently preliminary. The code adds some checks to the lock fast paths. Micro-benchmarks show little to no difference without RTM. This patch implements the low level "lll_" code for lock elision. Followon patches hook this into the pthread implementation Changes with the RTM mutexes: ----------------------------- Lock elision in pthreads is generally compatible with existing programs. There are some obscure exceptions, which are expected to be uncommon. See the manual for more details. - A broken program that unlocks a free lock will crash. There are ways around this with some tradeoffs (more code in hot paths) I'm still undecided on what approach to take here; have to wait for testing reports. - pthread_mutex_destroy of a lock mutex will not return EBUSY but 0. - There's also a similar situation with trylock outside the mutex, "knowing" that the mutex must be held due to some other condition. In this case an assert failure cannot be recovered. This situation is usually an existing bug in the program. - Same applies to the rwlocks. Some of the return values changes (for example there is no EDEADLK for an elided lock, unless it aborts. However when elided it will also never deadlock of course) - Timing changes, so broken programs that make assumptions about specific timing may expose already existing latent problems. Note that these broken programs will break in other situations too (loaded system, new faster hardware, compiler optimizations etc.) - Programs with non recursive mutexes that take them recursively in a thread and which would always deadlock without elision may not always see a deadlock. The deadlock will only happen on an early or delayed abort (which typically happens at some point) This only happens for mutexes not explicitely set to PTHREAD_MUTEX_NORMAL or PTHREAD_MUTEX_ADAPTIVE_NP. PTHREAD_MUTEX_NORMAL mutexes do not elide. The elision default can be set at configure time. This patch implements the basic infrastructure for elision.
* Enable static 32-bit SSE4.2 strcasecmp/strncasecmpH.J. Lu2013-07-023-6/+6
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* Implement fma in soft-fp.Joseph Myers2013-07-0221-109/+681
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* ARM: Pass dl_hwcap to IFUNC resolver functions.Will Newton2013-07-022-1/+6
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* Support no-FPU ColdFire in sysdeps/m68k/dl-trampoline.S and refactor code.Joseph Myers2013-06-302-24/+27
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* tile: switch to using <fenv.h> fallback functionsChris Metcalf2013-06-307-165/+9
| | | | | Now that the fallback functions match the desired semantics for tile functions, just switch to using them.
* Add more NEWS items for 2.18.Joseph Myers2013-06-281-0/+15
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* Skip SSE4.2 versions on Intel SilvermontLiubov Dmitrieva2013-06-286-15/+51
| | | | SSE2/SSSE3 versions are faster than SSE4.2 versions on Intel Silvermont.
* PowerPC: Define AT_HWCAP2 bits and AT_HWCAP2 handling for POWER8.Ryan S. Arnold2013-06-286-22/+85
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* Add GLRO(dl_hwcap2) for new AT_HWCAP2 auxv_t a_type.Ryan S. Arnold2013-06-2818-13/+89
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* Consistently use page_shift in sysdeps/unix/sysv/linux/mmap64.c.Joseph Myers2013-06-282-1/+6
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* Test for mprotect failure in dl-load.c (bug 12492).Pierre Ynard2013-06-283-13/+23
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* Mark packed structure element used with atomic operation aligned.Nathan Froyd2013-06-282-1/+18
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