diff options
Diffstat (limited to 'sysdeps')
| -rw-r--r-- | sysdeps/s390/configure | 36 | ||||
| -rw-r--r-- | sysdeps/s390/configure.ac | 26 | ||||
| -rw-r--r-- | sysdeps/s390/fpu/fraiseexcpt.c | 41 | ||||
| -rw-r--r-- | sysdeps/s390/fpu/fsetexcptflg.c | 3 |
4 files changed, 100 insertions, 6 deletions
diff --git a/sysdeps/s390/configure b/sysdeps/s390/configure index c9fb69cd6c..347ac28528 100644 --- a/sysdeps/s390/configure +++ b/sysdeps/s390/configure @@ -177,5 +177,41 @@ then fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for S390 z196 zarch instruction support as default" >&5 +$as_echo_n "checking for S390 z196 zarch instruction support as default... " >&6; } +if ${libc_cv_asm_s390_min_z196_zarch+:} false; then : + $as_echo_n "(cached) " >&6 +else + cat > conftest.c <<\EOF +float testinsn (double e) +{ + float d; + __asm__ ("ledbra %0,5,%1,4" : "=f" (d) : "f" (e) ); + return d; +} +EOF +if { ac_try='${CC-cc} $CFLAGS $CPPFLAGS $LDFLAGS --shared conftest.c + -o conftest.o &> /dev/null' + { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5 + (eval $ac_try) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; } ; +then + libc_cv_asm_s390_min_z196_zarch=yes +else + libc_cv_asm_s390_min_z196_zarch=no +fi +rm -f conftest* +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libc_cv_asm_s390_min_z196_zarch" >&5 +$as_echo "$libc_cv_asm_s390_min_z196_zarch" >&6; } + +if test "$libc_cv_asm_s390_min_z196_zarch" = yes ; +then + $as_echo "#define HAVE_S390_MIN_Z196_ZARCH_ASM_SUPPORT 1" >>confdefs.h + +fi + test -n "$critic_missing" && as_fn_error $? " *** $critic_missing" "$LINENO" 5 diff --git a/sysdeps/s390/configure.ac b/sysdeps/s390/configure.ac index 1db6d84a20..8a782e7c3a 100644 --- a/sysdeps/s390/configure.ac +++ b/sysdeps/s390/configure.ac @@ -86,5 +86,31 @@ then AC_DEFINE(HAVE_S390_VX_GCC_SUPPORT) fi +AC_CACHE_CHECK(for S390 z196 zarch instruction support as default, + libc_cv_asm_s390_min_z196_zarch, [dnl +cat > conftest.c <<\EOF +float testinsn (double e) +{ + float d; + __asm__ ("ledbra %0,5,%1,4" : "=f" (d) : "f" (e) ); + return d; +} +EOF +dnl +dnl test, if assembler supports S390 z196 zarch instructions as default +if AC_TRY_COMMAND([${CC-cc} $CFLAGS $CPPFLAGS $LDFLAGS --shared conftest.c + -o conftest.o &> /dev/null]) ; +then + libc_cv_asm_s390_min_z196_zarch=yes +else + libc_cv_asm_s390_min_z196_zarch=no +fi +rm -f conftest* ]) + +if test "$libc_cv_asm_s390_min_z196_zarch" = yes ; +then + AC_DEFINE(HAVE_S390_MIN_Z196_ZARCH_ASM_SUPPORT) +fi + test -n "$critic_missing" && AC_MSG_ERROR([ *** $critic_missing]) diff --git a/sysdeps/s390/fpu/fraiseexcpt.c b/sysdeps/s390/fpu/fraiseexcpt.c index 92a1a7db68..ac6dfe7739 100644 --- a/sysdeps/s390/fpu/fraiseexcpt.c +++ b/sysdeps/s390/fpu/fraiseexcpt.c @@ -35,6 +35,23 @@ fexceptadd (float d, float e) __asm__ __volatile__ ("aebr %0,%1" : : "f" (d), "f" (e) ); } +#ifdef HAVE_S390_MIN_Z196_ZARCH_ASM_SUPPORT +static __inline__ void +fexceptround (double e) +{ + float d; + /* Load rounded from double to float with M3 = round toward 0, M4 = Suppress + IEEE-inexact exception. + In case of e=0x1p128 and the overflow-mask bit is zero, only the + IEEE-overflow flag is set. If overflow-mask bit is one, DXC field is set to + 0x20 "IEEE overflow, exact". + In case of e=0x1p-150 and the underflow-mask bit is zero, only the + IEEE-underflow flag is set. If underflow-mask bit is one, DXC field is set + to 0x10 "IEEE underflow, exact". + This instruction is available with a zarch machine >= z196. */ + __asm__ __volatile__ ("ledbra %0,5,%1,4" : "=f" (d) : "f" (e) ); +} +#endif int __feraiseexcept (int excepts) @@ -54,13 +71,29 @@ __feraiseexcept (int excepts) /* Next: overflow. */ if (FE_OVERFLOW & excepts) - /* I don't think we can do the same trick as intel so we will have - to live with inexact coming also. */ - fexceptadd (FLT_MAX, 1.0e32); + { +#ifdef HAVE_S390_MIN_Z196_ZARCH_ASM_SUPPORT + fexceptround (0x1p128); +#else + /* If overflow-mask bit is zero, both IEEE-overflow and IEEE-inexact flags + are set. If overflow-mask bit is one, DXC field is set to 0x2C "IEEE + overflow, inexact and incremented". */ + fexceptadd (FLT_MAX, 1.0e32); +#endif + } /* Next: underflow. */ if (FE_UNDERFLOW & excepts) - fexceptdiv (FLT_MIN, 3.0); + { +#ifdef HAVE_S390_MIN_Z196_ZARCH_ASM_SUPPORT + fexceptround (0x1p-150); +#else + /* If underflow-mask bit is zero, both IEEE-underflow and IEEE-inexact + flags are set. If underflow-mask bit is one, DXC field is set to 0x1C + "IEEE underflow, inexact and incremented". */ + fexceptdiv (FLT_MIN, 3.0); +#endif + } /* Last: inexact. */ if (FE_INEXACT & excepts) diff --git a/sysdeps/s390/fpu/fsetexcptflg.c b/sysdeps/s390/fpu/fsetexcptflg.c index 25ade854bd..56a52c6bb7 100644 --- a/sysdeps/s390/fpu/fsetexcptflg.c +++ b/sysdeps/s390/fpu/fsetexcptflg.c @@ -45,8 +45,7 @@ fesetexceptflag (const fexcept_t *flagp, int excepts) & newexcepts; /* Store the new status word (along with the rest of the environment. - Possibly new exceptions are set but they won't get executed unless - the next floating-point instruction. */ + Possibly new exceptions are set but they won't get executed. */ _FPU_SETCW (temp); /* Success. */ |