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-rw-r--r--sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext.S9
-rw-r--r--sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext.S4
-rw-r--r--sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext.S13
-rw-r--r--sysdeps/unix/sysv/linux/powerpc/powerpc64/getcontext.S24
-rw-r--r--sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S4
-rw-r--r--sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S25
6 files changed, 31 insertions, 48 deletions
diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext.S b/sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext.S
index 447a18b2c7..6e4bc63b1a 100644
--- a/sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext.S
+++ b/sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext.S
@@ -187,8 +187,8 @@ ENTRY(__getcontext)
 	addi  r9,r9,32
 
 	stvx  v18,0,r10
-	stvx  v11,0,r9
-	addi  r19,r10,32
+	stvx  v19,0,r9
+	addi  r10,r10,32
 	addi  r9,r9,32
 
 	stvx  v20,0,r10
@@ -221,11 +221,6 @@ ENTRY(__getcontext)
 	addi  r10,r10,32
 	addi  r9,r9,32
 
-	stvx  v10,0,r10
-	stvx  v11,0,r9
-	addi  r10,r10,32
-	addi  r9,r9,32
-
 	mfvscr	v0
 	mfspr	r0,VRSAVE
 	stvx	v0,0,r10
diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext.S b/sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext.S
index 8d31326875..464155aefb 100644
--- a/sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext.S
+++ b/sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext.S
@@ -133,8 +133,8 @@ ENTRY(__setcontext)
 	addi  r9,r9,32
 
 	lvx   v18,0,r10
-	lvx   v11,0,r9
-	addi  r19,r10,32
+	lvx   v19,0,r9
+	addi  r10,r10,32
 	addi  r9,r9,32
 
 	lvx   v20,0,r10
diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext.S b/sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext.S
index 9d4c9bc1f6..af54e18878 100644
--- a/sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext.S
+++ b/sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext.S
@@ -189,8 +189,8 @@ ENTRY(__swapcontext)
 	addi  r9,r9,32
 
 	stvx  v18,0,r10
-	stvx  v11,0,r9
-	addi  r19,r10,32
+	stvx  v19,0,r9
+	addi  r10,r10,32
 	addi  r9,r9,32
 
 	stvx  v20,0,r10
@@ -223,11 +223,6 @@ ENTRY(__swapcontext)
 	addi  r10,r10,32
 	addi  r9,r9,32
 
-	stvx  v10,0,r10
-	stvx  v11,0,r9
-	addi  r10,r10,32
-	addi  r9,r9,32
-
 	mfvscr	v0
 	mfspr	r0,VRSAVE
 	stvx	v0,0,r10
@@ -339,8 +334,8 @@ L(no_vec):
 	addi  r9,r9,32
 
 	lvx   v18,0,r10
-	lvx   v11,0,r9
-	addi  r19,r10,32
+	lvx   v19,0,r9
+	addi  r10,r10,32
 	addi  r9,r9,32
 
 	lvx   v20,0,r10
diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc64/getcontext.S b/sysdeps/unix/sysv/linux/powerpc/powerpc64/getcontext.S
index 9deded79c7..851a171fa3 100644
--- a/sysdeps/unix/sysv/linux/powerpc/powerpc64/getcontext.S
+++ b/sysdeps/unix/sysv/linux/powerpc/powerpc64/getcontext.S
@@ -268,21 +268,22 @@ ENTRY(__getcontext)
   stfd  fp0,(SIGCONTEXT_FP_REGS+(32*8))(r3)
 
   ld    r5,.LC__dl_hwcap@toc(r2)
-  li    r10,0
 # ifdef SHARED
 /* Load _rtld-global._dl_hwcap.  */
   ld    r5,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r5)
 # else
   ld    r5,0(r5) /* Load extern _dl_hwcap.  */
-# endif
-  andis.  r5,r5,(PPC_FEATURE_HAS_ALTIVEC >> 16)
-  beq   L(has_no_vec)
-
+# endif  
   la    r10,(SIGCONTEXT_V_RESERVE+8)(r3)
   la    r9,(SIGCONTEXT_V_RESERVE+24)(r3)
+  
+  andis.  r5,r5,(PPC_FEATURE_HAS_ALTIVEC >> 16)
+  
   clrrdi  r10,r10,4
+  beq   L(has_no_vec)
   clrrdi  r9,r9,4
-
+  mr    r5,r10	/* Capture *v_regs value in r5.  */
+  
   stvx  v0,0,r10
   stvx  v1,0,r9
   addi  r10,r10,32
@@ -329,8 +330,8 @@ ENTRY(__getcontext)
   addi  r9,r9,32
 
   stvx  v18,0,r10
-  stvx  v11,0,r9
-  addi  r19,r10,32
+  stvx  v19,0,r9
+  addi  r10,r10,32
   addi  r9,r9,32
 
   stvx  v20,0,r10
@@ -363,11 +364,6 @@ ENTRY(__getcontext)
   addi  r10,r10,32
   addi  r9,r9,32
 
-  stvx  v10,0,r10
-  stvx  v11,0,r9
-  addi  r10,r10,32
-  addi  r9,r9,32
-
   mfvscr  v0
   mfspr r0,VRSAVE
   stvx  v0,0,r10
@@ -378,7 +374,7 @@ L(has_no_vec):
    Store either a NULL or a quadword aligned pointer to the Vector register
    array into *v_regs.
 */
-  std   r10,(SIGCONTEXT_V_REGS_PTR)(r3)
+  std   r5,(SIGCONTEXT_V_REGS_PTR)(r3)
 
   addi  r5,r3,UCONTEXT_SIGMASK
   li  r4,0
diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S b/sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S
index a07a750ec7..278489fb36 100644
--- a/sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S
+++ b/sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S
@@ -293,8 +293,8 @@ ENTRY(__setcontext)
   addi  r9,r9,32
 
   lvx   v18,0,r10
-  lvx   v11,0,r9
-  addi  r19,r10,32
+  lvx   v19,0,r9
+  addi  r10,r10,32
   addi  r9,r9,32
 
   lvx   v20,0,r10
diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S b/sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S
index 0f978512d4..ad1ba6963b 100644
--- a/sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S
+++ b/sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S
@@ -391,20 +391,22 @@ ENTRY(__swapcontext)
   stfd  fp0,(SIGCONTEXT_FP_REGS+(32*8))(r3)
 
   ld    r8,.LC__dl_hwcap@toc(r2)
-  li    r10,0
 #ifdef SHARED
 /* Load _rtld-global._dl_hwcap.  */
   ld    r8,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r8)
 #else
   ld    r8,0(r8) /* Load extern _dl_hwcap.  */
 #endif
-  andis.  r8,r8,(PPC_FEATURE_HAS_ALTIVEC >> 16)
-  beq   L(has_no_vec)
-
   la    r10,(SIGCONTEXT_V_RESERVE+8)(r3)
   la    r9,(SIGCONTEXT_V_RESERVE+24)(r3)
+  
+  andis.  r8,r8,(PPC_FEATURE_HAS_ALTIVEC >> 16)
+
   clrrdi  r10,r10,4
+  beq   L(has_no_vec)
+  
   clrrdi  r9,r9,4
+  mr    r8,r10	/* Capture *v_regs value in r5.  */
 
   stvx  v0,0,r10
   stvx  v1,0,r9
@@ -452,8 +454,8 @@ ENTRY(__swapcontext)
   addi  r9,r9,32
 
   stvx  v18,0,r10
-  stvx  v11,0,r9
-  addi  r19,r10,32
+  stvx  v19,0,r9
+  addi  r10,r10,32
   addi  r9,r9,32
 
   stvx  v20,0,r10
@@ -486,11 +488,6 @@ ENTRY(__swapcontext)
   addi  r10,r10,32
   addi  r9,r9,32
 
-  stvx  v10,0,r10
-  stvx  v11,0,r9
-  addi  r10,r10,32
-  addi  r9,r9,32
-
   mfvscr  v0
   mfspr r0,VRSAVE
   stvx  v0,0,r10
@@ -501,7 +498,7 @@ L(has_no_vec):
    Store either a NULL or a quadword aligned pointer to the Vector register
    array into *v_regs.
 */
-  std   r10,(SIGCONTEXT_V_REGS_PTR)(r3)
+  std   r8,(SIGCONTEXT_V_REGS_PTR)(r3)
 
   mr    r31,r4
   addi  r5,r3,UCONTEXT_SIGMASK
@@ -596,8 +593,8 @@ L(has_no_vec):
   addi  r9,r9,32
 
   lvx   v18,0,r10
-  lvx   v11,0,r9
-  addi  r19,r10,32
+  lvx   v19,0,r9
+  addi  r10,r10,32
   addi  r9,r9,32
 
   lvx   v20,0,r10