about summary refs log tree commit diff
path: root/sysdeps/x86_64/cacheinfo.c
diff options
context:
space:
mode:
Diffstat (limited to 'sysdeps/x86_64/cacheinfo.c')
-rw-r--r--sysdeps/x86_64/cacheinfo.c23
1 files changed, 23 insertions, 0 deletions
diff --git a/sysdeps/x86_64/cacheinfo.c b/sysdeps/x86_64/cacheinfo.c
index f1cbf50957..b99fb9a762 100644
--- a/sysdeps/x86_64/cacheinfo.c
+++ b/sysdeps/x86_64/cacheinfo.c
@@ -585,6 +585,10 @@ init_cacheinfo (void)
       __cpuid (1, eax, ebx_1, ecx, edx);
 #endif
 
+      unsigned int family = (eax >> 8) & 0x0f;
+      unsigned int model = (eax >> 4) & 0x0f;
+      unsigned int extended_model = (eax >> 12) & 0xf0;
+
 #ifndef DISABLE_PREFERRED_MEMORY_INSTRUCTION
       /* Intel prefers SSSE3 instructions for memory/string routines
 	 if they are available.  */
@@ -647,6 +651,25 @@ init_cacheinfo (void)
 		}
 	    }
 	  threads += 1;
+	  if (threads > 2 && level == 2 && family == 6)
+	    {
+	      model += extended_model;
+	      switch (model)
+		{
+		case 0x57:
+		  /* Knights Landing has L2 cache shared by 2 cores.  */
+		case 0x37:
+		case 0x4a:
+		case 0x4d:
+		case 0x5a:
+		case 0x5d:
+		  /* Silvermont has L2 cache shared by 2 cores.  */
+		  threads = 2;
+		  break;
+		default:
+		  break;
+		}
+	    }
 	}
       else
 	{