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-rw-r--r--sysdeps/sparc/sparc32/Versions (renamed from sysdeps/sparc/Versions)0
-rw-r--r--sysdeps/sparc/sparc64/Versions7
-rw-r--r--sysdeps/sparc/sparc64/bits/wordsize.h23
-rw-r--r--sysdeps/sparc/sparc64/fpu/bits/fenv.h17
-rw-r--r--sysdeps/sparc/sparc64/fpu/fpu_control.h9
-rw-r--r--sysdeps/sparc/sparc64/memcpy.S73
6 files changed, 124 insertions, 5 deletions
diff --git a/sysdeps/sparc/Versions b/sysdeps/sparc/sparc32/Versions
index aa36082e9e..aa36082e9e 100644
--- a/sysdeps/sparc/Versions
+++ b/sysdeps/sparc/sparc32/Versions
diff --git a/sysdeps/sparc/sparc64/Versions b/sysdeps/sparc/sparc64/Versions
new file mode 100644
index 0000000000..99fe741a12
--- /dev/null
+++ b/sysdeps/sparc/sparc64/Versions
@@ -0,0 +1,7 @@
+libc {
+  GLIBC_2.1.1 {
+    # SPARC v9 SYSV ABI helper functions
+    __align_cpy_1; __align_cpy_2; __align_cpy_4;
+    __align_cpy_8; __align_cpy_16;
+  }
+}
diff --git a/sysdeps/sparc/sparc64/bits/wordsize.h b/sysdeps/sparc/sparc64/bits/wordsize.h
new file mode 100644
index 0000000000..f86b7f7fbf
--- /dev/null
+++ b/sysdeps/sparc/sparc64/bits/wordsize.h
@@ -0,0 +1,23 @@
+/* Copyright (C) 1999 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Library General Public License as
+   published by the Free Software Foundation; either version 2 of the
+   License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Library General Public License for more details.
+
+   You should have received a copy of the GNU Library General Public
+   License along with the GNU C Library; see the file COPYING.LIB.  If not,
+   write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+   Boston, MA 02111-1307, USA.  */
+
+#if defined __sparc_v9__ || defined __arch64__ || defined __sparcv9
+# define __WORDSIZE	64
+#else
+# define __WORDSIZE	32
+#endif
diff --git a/sysdeps/sparc/sparc64/fpu/bits/fenv.h b/sysdeps/sparc/sparc64/fpu/bits/fenv.h
index b864abdedf..af8ed65768 100644
--- a/sysdeps/sparc/sparc64/fpu/bits/fenv.h
+++ b/sysdeps/sparc/sparc64/fpu/bits/fenv.h
@@ -1,4 +1,4 @@
-/* Copyright (C) 1997, 1998 Free Software Foundation, Inc.
+/* Copyright (C) 1997, 1998, 1999 Free Software Foundation, Inc.
    This file is part of the GNU C Library.
 
    The GNU C Library is free software; you can redistribute it and/or
@@ -20,6 +20,8 @@
 # error "Never use <bits/fenv.h> directly; include <fenv.h> instead."
 #endif
 
+#include <bits/wordsize.h>
+
 
 /* Define bits representing the exception.  We use the bit positions
    of the appropriate accrued exception bits from the FSR.  */
@@ -57,11 +59,19 @@ enum
 
 #define __FE_ROUND_MASK	(3U << 30)
 
+#if __WORDSIZE == 64
 /* Type representing exception flags.  */
 typedef unsigned long fexcept_t;
 
 /* Type representing floating-point environment.  */
 typedef unsigned long fenv_t;
+#else
+/* Type representing exception flags.  */
+typedef unsigned int fexcept_t;
+
+/* Type representing floating-point environment.  */
+typedef unsigned int fenv_t;
+#endif
 
 /* If the default argument is used we use this value.  */
 #define FE_DFL_ENV	((fenv_t *) -1)
@@ -72,5 +82,10 @@ typedef unsigned long fenv_t;
 #endif
 
 /* For internal use only: access the fp state register.  */
+#if __WORDSIZE == 64
 #define __fenv_stfsr(X)   __asm__ ("stx %%fsr,%0" : "=m" (X))
 #define __fenv_ldfsr(X)   __asm__ __volatile__ ("ldx %0,%%fsr" : : "m" (X))
+#else
+#define __fenv_stfsr(X)   __asm__ ("st %%fsr,%0" : "=m" (X))
+#define __fenv_ldfsr(X)   __asm__ __volatile__ ("ld %0,%%fsr" : : "m" (X))
+#endif
diff --git a/sysdeps/sparc/sparc64/fpu/fpu_control.h b/sysdeps/sparc/sparc64/fpu/fpu_control.h
index b684fa934e..a89f00eed5 100644
--- a/sysdeps/sparc/sparc64/fpu/fpu_control.h
+++ b/sysdeps/sparc/sparc64/fpu/fpu_control.h
@@ -23,6 +23,7 @@
 
 
 #include <features.h>
+#include <bits/wordsize.h>
 
 /* masking of interrupts */
 #define _FPU_MASK_IM  0x08000000
@@ -55,11 +56,19 @@
 #define _FPU_DEFAULT  0x0
 #define _FPU_IEEE     0x0
 
+#if __WORDSIZE == 64
 /* Type of the control word.  */
 typedef unsigned long fpu_control_t;
 
 #define _FPU_GETCW(cw) __asm__ ("stx %%fsr,%0" : "=m" (*&cw))
 #define _FPU_SETCW(cw) __asm__ ("ldx %0,%%fsr" : : "m" (*&cw))
+#else
+/* Type of the control word.  */
+typedef unsigned int fpu_control_t;
+
+#define _FPU_GETCW(cw) __asm__ ("st %%fsr,%0" : "=m" (*&cw))
+#define _FPU_SETCW(cw) __asm__ ("ld %0,%%fsr" : : "m" (*&cw))
+#endif
 
 /* Default control word set at startup.  */
 extern fpu_control_t __fpu_control;
diff --git a/sysdeps/sparc/sparc64/memcpy.S b/sysdeps/sparc/sparc64/memcpy.S
index fa08507d0c..180ff23e20 100644
--- a/sysdeps/sparc/sparc64/memcpy.S
+++ b/sysdeps/sparc/sparc64/memcpy.S
@@ -380,6 +380,66 @@ END(bcopy)
 209:	retl
 	 mov		%g4, %o0
 
+#ifdef USE_BPR
+
+	/* void *__align_cpy_4(void *dest, void *src, size_t n)
+	 * SPARC v9 SYSV ABI
+	 * Like memcpy, but results are undefined if (!n || ((dest | src | n) & 3))
+	 */
+
+	.align		32
+ENTRY(__align_cpy_4)
+	mov		%o0, %g4			/* IEU0		Group		*/
+	cmp		%o2, 15				/* IEU1				*/
+	bleu,pn		%xcc, 208b			/* CTI				*/
+	 cmp		%o2, (64 * 6)			/* IEU1		Group		*/
+	bgeu,pn		%xcc, 200b			/* CTI				*/
+	 andcc		%o0, 7, %g2			/* IEU1		Group		*/
+	ba,pt		%xcc, 216f			/* CTI				*/
+	 andcc		%o1, 4, %g0			/* IEU1		Group		*/
+END(__align_cpy_4)
+
+	/* void *__align_cpy_8(void *dest, void *src, size_t n)
+	 * SPARC v9 SYSV ABI
+	 * Like memcpy, but results are undefined if (!n || ((dest | src | n) & 7))
+	 */
+
+	.align		32
+ENTRY(__align_cpy_8)
+	mov		%o0, %g4			/* IEU0		Group		*/
+	cmp		%o2, 15				/* IEU1				*/
+	bleu,pn		%xcc, 208b			/* CTI				*/
+	 cmp		%o2, (64 * 6)			/* IEU1		Group		*/
+	bgeu,pn		%xcc, 201b			/* CTI				*/
+	 andcc		%o0, 0x38, %g5			/* IEU1		Group		*/
+	andcc		%o2, -128, %g7			/* IEU1		Group		*/
+	bne,a,pt	%xcc, 82f + 4			/* CTI				*/
+	 ldx		[%o1], %g1			/* Load				*/
+	ba,pt		%xcc, 41f			/* CTI		Group		*/
+	 andcc		%o2, 0x70, %g7			/* IEU1				*/
+END(__align_cpy_8)
+
+	/* void *__align_cpy_16(void *dest, void *src, size_t n)
+	 * SPARC v9 SYSV ABI
+	 * Like memcpy, but results are undefined if (!n || ((dest | src | n) & 15))
+	 */
+
+	.align		32
+ENTRY(__align_cpy_16)
+	mov		%o0, %g4			/* IEU0		Group		*/
+	cmp		%o2, (64 * 6)			/* IEU1				*/
+	bgeu,pn		%xcc, 201b			/* CTI				*/
+	 andcc		%o0, 0x38, %g5			/* IEU1		Group		*/
+	andcc		%o2, -128, %g7			/* IEU1		Group		*/
+	bne,a,pt	%xcc, 82f + 4			/* CTI				*/
+	 ldx		[%o1], %g1			/* Load				*/
+	ba,pt		%xcc, 41f			/* CTI		Group		*/
+	 andcc		%o2, 0x70, %g7			/* IEU1				*/
+END(__align_cpy_16)
+
+#endif
+
+	.align		32
 ENTRY(memcpy)
 210:
 #ifndef USE_BPR
@@ -396,7 +456,7 @@ ENTRY(memcpy)
 	andcc		%g5, 3, %o5			/* IEU1		Group		*/
 	bne,pn		%xcc, 212f			/* CTI				*/
 	 andcc		%o1, 3, %g0			/* IEU1		Group		*/
-	be,a,pt		%xcc, 3f			/* CTI				*/
+	be,a,pt		%xcc, 216f			/* CTI				*/
 	 andcc		%o1, 4, %g0			/* IEU1		Group		*/
 	andcc		%o1, 1, %g0			/* IEU1		Group		*/
 	be,pn		%xcc, 4f			/* CTI				*/
@@ -413,7 +473,7 @@ ENTRY(memcpy)
 	sub		%o2, 2, %o2			/* IEU0				*/
 	sth		%g2, [%o0 - 2]			/* Store	Group + bubble	*/
 5:	andcc		%o1, 4, %g0			/* IEU1				*/
-3:	be,a,pn		%xcc, 2f			/* CTI				*/
+216:	be,a,pn		%xcc, 2f			/* CTI				*/
 	 andcc		%o2, -128, %g7			/* IEU1		Group		*/
 	lduw		[%o1], %g5			/* Load		Group		*/
 	add		%o1, 4, %o1			/* IEU0				*/
@@ -421,7 +481,7 @@ ENTRY(memcpy)
 	sub		%o2, 4, %o2			/* IEU0		Group		*/
 	stw		%g5, [%o0 - 4]			/* Store			*/
 	andcc		%o2, -128, %g7			/* IEU1		Group		*/
-2:	be,pn		%xcc, 3f			/* CTI				*/
+2:	be,pn		%xcc, 215f			/* CTI				*/
 	 andcc		%o0, 4, %g0			/* IEU1		Group		*/
 	be,pn		%xcc, 82f + 4			/* CTI		Group		*/
 5:	MOVE_BIGCHUNK(o1, o0, 0x00, g1, g3, g5, o5)
@@ -432,7 +492,7 @@ ENTRY(memcpy)
 	add		%o1, 128, %o1			/* IEU0				*/
 	bne,pt		%xcc, 5b			/* CTI				*/
 	 add		%o0, 128, %o0			/* IEU0		Group		*/
-3:	andcc		%o2, 0x70, %g7			/* IEU1		Group		*/
+215:	andcc		%o2, 0x70, %g7			/* IEU1		Group		*/
 41:	be,pn		%xcc, 80f			/* CTI				*/
 	 andcc		%o2, 8, %g0			/* IEU1		Group		*/
 							/* Clk1 8-(			*/
@@ -572,3 +632,8 @@ ENTRY(memcpy)
 	retl
 	 mov		%g4, %o0
 END(memcpy)
+
+#ifdef USE_BPR
+weak_alias(memcpy, __align_cpy_1)
+weak_alias(memcpy, __align_cpy_2)
+#endif