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-rw-r--r--sysdeps/mips/mips32/sfp-machine.h4
-rw-r--r--sysdeps/mips/mips64/sfp-machine.h4
-rw-r--r--sysdeps/mips/sys/asm.h16
3 files changed, 12 insertions, 12 deletions
diff --git a/sysdeps/mips/mips32/sfp-machine.h b/sysdeps/mips/mips32/sfp-machine.h
index 5215655029..8fa429a67e 100644
--- a/sysdeps/mips/mips32/sfp-machine.h
+++ b/sysdeps/mips/mips32/sfp-machine.h
@@ -56,8 +56,8 @@
    NaNs is sNaN,  in which case the result is NANSIGN/NANFRAC.  */
 # define _FP_CHOOSENAN(fs, wc, R, X, Y, OP)			\
   do {								\
-    if ((_FP_FRAC_HIGH_RAW_##fs(X) |				\
-	 _FP_FRAC_HIGH_RAW_##fs(Y)) & _FP_QNANBIT_##fs)		\
+    if ((_FP_FRAC_HIGH_RAW_##fs(X)				\
+	 | _FP_FRAC_HIGH_RAW_##fs(Y)) & _FP_QNANBIT_##fs)	\
       {								\
 	R##_s = _FP_NANSIGN_##fs;				\
         _FP_FRAC_SET_##wc(R,_FP_NANFRAC_##fs);			\
diff --git a/sysdeps/mips/mips64/sfp-machine.h b/sysdeps/mips/mips64/sfp-machine.h
index c769ee81f6..4d1f90fc9b 100644
--- a/sysdeps/mips/mips64/sfp-machine.h
+++ b/sysdeps/mips/mips64/sfp-machine.h
@@ -59,8 +59,8 @@
    NaNs is sNaN,  in which case the result is NANSIGN/NANFRAC.  */
 # define _FP_CHOOSENAN(fs, wc, R, X, Y, OP)			\
   do {								\
-    if ((_FP_FRAC_HIGH_RAW_##fs(X) |				\
-	 _FP_FRAC_HIGH_RAW_##fs(Y)) & _FP_QNANBIT_##fs)		\
+    if ((_FP_FRAC_HIGH_RAW_##fs(X)				\
+	 | _FP_FRAC_HIGH_RAW_##fs(Y)) & _FP_QNANBIT_##fs)	\
       {								\
 	R##_s = _FP_NANSIGN_##fs;				\
         _FP_FRAC_SET_##wc(R,_FP_NANFRAC_##fs);			\
diff --git a/sysdeps/mips/sys/asm.h b/sysdeps/mips/sys/asm.h
index a7fdcc0a7f..f6ec1e7c3d 100644
--- a/sysdeps/mips/sys/asm.h
+++ b/sysdeps/mips/sys/asm.h
@@ -232,8 +232,8 @@ symbol		=	value
  * MIPS IV implementations are free to treat this as a nop.  The R5000
  * is one of them.  So we should have an option not to use this instruction.
  */
-#if (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
-    (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
+#if (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) \
+    || (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
 # define PREF(hint,addr)                                 \
 		pref	hint,addr
 # define PREFX(hint,addr)                                \
@@ -278,8 +278,8 @@ symbol		=	value
 		.set	pop;				\
 9:
 #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
-#if (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
-    (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
+#if (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) \
+    || (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
 # define MOVN(rd,rs,rt)					\
 		movn	rd,rs,rt
 # define MOVZ(rd,rs,rt)					\
@@ -468,13 +468,13 @@ symbol		=	value
 /*
  * Some cp0 registers were extended to 64bit for MIPS III.
  */
-#if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \
-    (_MIPS_ISA == _MIPS_ISA_MIPS32)
+#if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) \
+    || (_MIPS_ISA == _MIPS_ISA_MIPS32)
 # define MFC0	mfc0
 # define MTC0	mtc0
 #endif
-#if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
-    (_MIPS_ISA == _MIPS_ISA_MIPS5) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
+#if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) \
+    || (_MIPS_ISA == _MIPS_ISA_MIPS5) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
 # define MFC0	dmfc0
 # define MTC0	dmtc0
 #endif