diff options
Diffstat (limited to 'sysdeps/microblaze/bits')
| -rw-r--r-- | sysdeps/microblaze/bits/atomic.h | 269 | ||||
| -rw-r--r-- | sysdeps/microblaze/bits/endian.h | 30 | ||||
| -rw-r--r-- | sysdeps/microblaze/bits/fenv.h | 42 | ||||
| -rw-r--r-- | sysdeps/microblaze/bits/link.h | 57 | ||||
| -rw-r--r-- | sysdeps/microblaze/bits/setjmp.h | 37 |
5 files changed, 435 insertions, 0 deletions
diff --git a/sysdeps/microblaze/bits/atomic.h b/sysdeps/microblaze/bits/atomic.h new file mode 100644 index 0000000000..77004a0284 --- /dev/null +++ b/sysdeps/microblaze/bits/atomic.h @@ -0,0 +1,269 @@ +/* Copyright (C) 2003-2014 Free Software Foundation, Inc. + + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library. If not, see + <http://www.gnu.org/licenses/>. */ + +#include <stdint.h> +#include <sysdep.h> + + +typedef int8_t atomic8_t; +typedef uint8_t uatomic8_t; +typedef int_fast8_t atomic_fast8_t; +typedef uint_fast8_t uatomic_fast8_t; + +typedef int32_t atomic32_t; +typedef uint32_t uatomic32_t; +typedef int_fast32_t atomic_fast32_t; +typedef uint_fast32_t uatomic_fast32_t; + +typedef intptr_t atomicptr_t; +typedef uintptr_t uatomicptr_t; +typedef intmax_t atomic_max_t; +typedef uintmax_t uatomic_max_t; + + +/* Microblaze does not have byte and halfword forms of load and reserve and + store conditional. So for microblaze we stub out the 8- and 16-bit forms. */ +#define __arch_compare_and_exchange_bool_8_acq(mem, newval, oldval) \ + (abort (), 0) + +#define __arch_compare_and_exchange_bool_16_acq(mem, newval, oldval) \ + (abort (), 0) + +#define __arch_compare_and_exchange_bool_8_rel(mem, newval, oldval) \ + (abort (), 0) + +#define __arch_compare_and_exchange_bool_16_rel(mem, newval, oldval) \ + (abort (), 0) + +#define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \ + ({ \ + __typeof (*(mem)) __tmp; \ + __typeof (mem) __memp = (mem); \ + int test; \ + __asm __volatile ( \ + " addc r0, r0, r0;" \ + "1: lwx %0, %3, r0;" \ + " addic %1, r0, 0;" \ + " bnei %1, 1b;" \ + " cmp %1, %0, %4;" \ + " bnei %1, 2f;" \ + " swx %5, %3, r0;" \ + " addic %1, r0, 0;" \ + " bnei %1, 1b;" \ + "2:" \ + : "=&r" (__tmp), \ + "=&r" (test), \ + "=m" (*__memp) \ + : "r" (__memp), \ + "r" (oldval), \ + "r" (newval) \ + : "cc", "memory"); \ + __tmp; \ + }) + +#define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \ + (abort (), (__typeof (*mem)) 0) + +#define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \ + ({ \ + __typeof (*(mem)) __result; \ + if (sizeof (*mem) == 4) \ + __result = __arch_compare_and_exchange_val_32_acq (mem, newval, oldval); \ + else if (sizeof (*mem) == 8) \ + __result = __arch_compare_and_exchange_val_64_acq (mem, newval, oldval); \ + else \ + abort (); \ + __result; \ + }) + +#define atomic_compare_and_exchange_val_rel(mem, newval, oldval) \ + ({ \ + __typeof (*(mem)) __result; \ + if (sizeof (*mem) == 4) \ + __result = __arch_compare_and_exchange_val_32_acq (mem, newval, oldval); \ + else if (sizeof (*mem) == 8) \ + __result = __arch_compare_and_exchange_val_64_acq (mem, newval, oldval); \ + else \ + abort (); \ + __result; \ + }) + +#define __arch_atomic_exchange_32_acq(mem, value) \ + ({ \ + __typeof (*(mem)) __tmp; \ + __typeof (mem) __memp = (mem); \ + int test; \ + __asm __volatile ( \ + " addc r0, r0, r0;" \ + "1: lwx %0, %4, r0;" \ + " addic %1, r0, 0;" \ + " bnei %1, 1b;" \ + " swx %3, %4, r0;" \ + " addic %1, r0, 0;" \ + " bnei %1, 1b;" \ + : "=&r" (__tmp), \ + "=&r" (test), \ + "=m" (*__memp) \ + : "r" (value), \ + "r" (__memp) \ + : "cc", "memory"); \ + __tmp; \ + }) + +#define __arch_atomic_exchange_64_acq(mem, newval) \ + (abort (), (__typeof (*mem)) 0) + +#define atomic_exchange_acq(mem, value) \ + ({ \ + __typeof (*(mem)) __result; \ + if (sizeof (*mem) == 4) \ + __result = __arch_atomic_exchange_32_acq (mem, value); \ + else if (sizeof (*mem) == 8) \ + __result = __arch_atomic_exchange_64_acq (mem, value); \ + else \ + abort (); \ + __result; \ + }) + +#define atomic_exchange_rel(mem, value) \ + ({ \ + __typeof (*(mem)) __result; \ + if (sizeof (*mem) == 4) \ + __result = __arch_atomic_exchange_32_acq (mem, value); \ + else if (sizeof (*mem) == 8) \ + __result = __arch_atomic_exchange_64_acq (mem, value); \ + else \ + abort (); \ + __result; \ + }) + +#define __arch_atomic_exchange_and_add_32(mem, value) \ + ({ \ + __typeof (*(mem)) __tmp; \ + __typeof (mem) __memp = (mem); \ + int test; \ + __asm __volatile ( \ + " addc r0, r0, r0;" \ + "1: lwx %0, %4, r0;" \ + " addic %1, r0, 0;" \ + " bnei %1, 1b;" \ + " add %1, %3, %0;" \ + " swx %1, %4, r0;" \ + " addic %1, r0, 0;" \ + " bnei %1, 1b;" \ + : "=&r" (__tmp), \ + "=&r" (test), \ + "=m" (*__memp) \ + : "r" (value), \ + "r" (__memp) \ + : "cc", "memory"); \ + __tmp; \ + }) + +#define __arch_atomic_exchange_and_add_64(mem, value) \ + (abort (), (__typeof (*mem)) 0) + +#define atomic_exchange_and_add(mem, value) \ + ({ \ + __typeof (*(mem)) __result; \ + if (sizeof (*mem) == 4) \ + __result = __arch_atomic_exchange_and_add_32 (mem, value); \ + else if (sizeof (*mem) == 8) \ + __result = __arch_atomic_exchange_and_add_64 (mem, value); \ + else \ + abort (); \ + __result; \ + }) + +#define __arch_atomic_increment_val_32(mem) \ + ({ \ + __typeof (*(mem)) __val; \ + int test; \ + __asm __volatile ( \ + " addc r0, r0, r0;" \ + "1: lwx %0, %3, r0;" \ + " addic %1, r0, 0;" \ + " bnei %1, 1b;" \ + " addi %0, %0, 1;" \ + " swx %0, %3, r0;" \ + " addic %1, r0, 0;" \ + " bnei %1, 1b;" \ + : "=&r" (__val), \ + "=&r" (test), \ + "=m" (*mem) \ + : "r" (mem), \ + "m" (*mem) \ + : "cc", "memory"); \ + __val; \ + }) + +#define __arch_atomic_increment_val_64(mem) \ + (abort (), (__typeof (*mem)) 0) + +#define atomic_increment_val(mem) \ + ({ \ + __typeof (*(mem)) __result; \ + if (sizeof (*(mem)) == 4) \ + __result = __arch_atomic_increment_val_32 (mem); \ + else if (sizeof (*(mem)) == 8) \ + __result = __arch_atomic_increment_val_64 (mem); \ + else \ + abort (); \ + __result; \ + }) + +#define atomic_increment(mem) ({ atomic_increment_val (mem); (void) 0; }) + +#define __arch_atomic_decrement_val_32(mem) \ + ({ \ + __typeof (*(mem)) __val; \ + int test; \ + __asm __volatile ( \ + " addc r0, r0, r0;" \ + "1: lwx %0, %3, r0;" \ + " addic %1, r0, 0;" \ + " bnei %1, 1b;" \ + " rsubi %0, %0, 1;" \ + " swx %0, %3, r0;" \ + " addic %1, r0, 0;" \ + " bnei %1, 1b;" \ + : "=&r" (__val), \ + "=&r" (test), \ + "=m" (*mem) \ + : "r" (mem), \ + "m" (*mem) \ + : "cc", "memory"); \ + __val; \ + }) + +#define __arch_atomic_decrement_val_64(mem) \ + (abort (), (__typeof (*mem)) 0) + +#define atomic_decrement_val(mem) \ + ({ \ + __typeof (*(mem)) __result; \ + if (sizeof (*(mem)) == 4) \ + __result = __arch_atomic_decrement_val_32 (mem); \ + else if (sizeof (*(mem)) == 8) \ + __result = __arch_atomic_decrement_val_64 (mem); \ + else \ + abort (); \ + __result; \ + }) + +#define atomic_decrement(mem) ({ atomic_decrement_val (mem); (void) 0; }) diff --git a/sysdeps/microblaze/bits/endian.h b/sysdeps/microblaze/bits/endian.h new file mode 100644 index 0000000000..49f000c4f7 --- /dev/null +++ b/sysdeps/microblaze/bits/endian.h @@ -0,0 +1,30 @@ +/* Copyright (C) 1997-2014 Free Software Foundation, Inc. + + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public License as + published by the Free Software Foundation; either version 2.1 of the + License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library. If not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _ENDIAN_H +# error "Never use <bits/endian.h> directly; include <endian.h> instead." +#endif + +/* MicroBlaze can be either big or little endian. */ +#ifdef _BIG_ENDIAN +# define __BYTE_ORDER __BIG_ENDIAN +# define __FLOAT_WORD_ORDER __BIG_ENDIAN +#else +# define __BYTE_ORDER __LITTLE_ENDIAN +# define __FLOAT_WORD_ORDER __LITTLE_ENDIAN +#endif diff --git a/sysdeps/microblaze/bits/fenv.h b/sysdeps/microblaze/bits/fenv.h new file mode 100644 index 0000000000..7622c258ee --- /dev/null +++ b/sysdeps/microblaze/bits/fenv.h @@ -0,0 +1,42 @@ +/* Copyright (C) 2011-2014 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library. If not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _FENV_H +# error "Never use <bits/fenv.h> directly; include <fenv.h> instead." +#endif + +/* MicroBlaze supports only round-to-nearest. The software + floating-point support also acts this way. */ +enum + { + __FE_UNDEFINED = 0, + + FE_TONEAREST = +#define FE_TONEAREST 0x1 + FE_TONEAREST, + }; + +#define FE_ALL_EXCEPT 0 + +/* Type representing exception flags (if there were any). */ +typedef unsigned int fexcept_t; + +/* Type representing floating-point environment. */ +typedef unsigned int fenv_t; + +/* If the default argument is used we use this value. */ +#define FE_DFL_ENV ((const fenv_t *) -1l) diff --git a/sysdeps/microblaze/bits/link.h b/sysdeps/microblaze/bits/link.h new file mode 100644 index 0000000000..588206e45d --- /dev/null +++ b/sysdeps/microblaze/bits/link.h @@ -0,0 +1,57 @@ +/* Copyright (C) 2005-2014 Free Software Foundation, Inc. + + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public License as + published by the Free Software Foundation; either version 2.1 of the + License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _LINK_H +# error "Never include <bits/link.h> directly; use <link.h> instead." +#endif + +/* Registers for entry into PLT on Microblaze. */ +typedef struct La_microblaze_regs +{ + uint32_t lr_r0; + uint32_t lr_r1; + uint32_t lr_sp; +} La_microblaze_regs; + +/* Return values for calls from PLT on Microblaze. */ +typedef struct La_microblaze_retval +{ + uint32_t lrv_r3; +} La_microblaze_retval; + + +__BEGIN_DECLS + +extern Elf32_Addr la_microblaze_gnu_pltenter (Elf32_Sym *__sym, + unsigned int __ndx, + uintptr_t *__refcook, + uintptr_t *__defcook, + La_microblaze_regs *__regs, + unsigned int *__flags, + const char *__symname, + long int *__framesizep); + +extern unsigned int la_microblaze_gnu_pltexit (Elf32_Sym *__sym, + unsigned int __ndx, + uintptr_t *__refcook, + uintptr_t *__defcook, + const La_microblaze_regs *__inregs, + La_microblaze_retval *__outregs, + const char *__symname); + +__END_DECLS diff --git a/sysdeps/microblaze/bits/setjmp.h b/sysdeps/microblaze/bits/setjmp.h new file mode 100644 index 0000000000..e90d6975b8 --- /dev/null +++ b/sysdeps/microblaze/bits/setjmp.h @@ -0,0 +1,37 @@ +/* Copyright (C) 1997-2014 Free Software Foundation, Inc. + + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public License as + published by the Free Software Foundation; either version 2.1 of the + License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +/* Define the machine-dependent type `jmp_buf'. */ + +#ifndef _BITS_SETJMP_H +# define _BITS_SETJMP_H 1 + +#if !defined _SETJMP_H && !defined _PTHREAD_H +# error "Never include <bits/setjmp.h> directly; use <setjmp.h> instead." +#endif + +typedef struct + { + /* There are 21 4-byte registers that should be saved: + r1, r2, r13-r31. Actually, there seems no need to save + r14, r16, r17, r18 (return addresses for interrupt/exception/trap). */ + int *__sp; /* dedicated name for r1. */ + long int __gregs[20]; + } __jmp_buf[1]; + +#endif |