diff options
Diffstat (limited to 'sysdeps/arm/fpu_control.h')
| -rw-r--r-- | sysdeps/arm/fpu_control.h | 61 |
1 files changed, 53 insertions, 8 deletions
diff --git a/sysdeps/arm/fpu_control.h b/sysdeps/arm/fpu_control.h index 054085d70a..8a2d338c49 100644 --- a/sysdeps/arm/fpu_control.h +++ b/sysdeps/arm/fpu_control.h @@ -1,5 +1,5 @@ -/* FPU control word definitions. Stub version. - Copyright (C) 1996, 1997 Free Software Foundation, Inc. +/* FPU control word definitions. ARM version. + Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. This file is part of the GNU C Library. The GNU C Library is free software; you can redistribute it and/or @@ -20,7 +20,54 @@ #ifndef _FPU_CONTROL_H #define _FPU_CONTROL_H -#define _FPU_RESERVED 0xffffffff /* These bits are reserved. */ +/* We have a slight terminology confusion here. On the ARM, the register + * we're interested in is actually the FPU status word - the FPU control + * word is something different (which is implementation-defined and only + * accessible from supervisor mode.) + * + * The FPSR looks like this: + * + * 31-24 23-16 15-8 7-0 + * | system ID | trap enable | system control | exception flags | + * + * We ignore the system ID bits; for interest's sake they are: + * + * 0000 "old" FPE + * 1000 FPPC hardware + * 0001 FPE 400 + * 1001 FPA hardware + * + * The trap enable and exception flags are both structured like this: + * + * 7 - 5 4 3 2 1 0 + * | reserved | INX | UFL | OFL | DVZ | IVO | + * + * where a `1' bit in the enable byte means that the trap can occur, and + * a `1' bit in the flags byte means the exception has occurred. + * + * The exceptions are: + * + * IVO - invalid operation + * DVZ - divide by zero + * OFL - overflow + * UFL - underflow + * INX - inexact (do not use; implementations differ) + * + * The system control byte looks like this: + * + * 7-5 4 3 2 1 0 + * | reserved | AC | EP | SO | NE | ND | + * + * where the bits mean + * + * ND - no denormalised numbers (force them all to zero) + * NE - enable NaN exceptions + * SO - synchronous operation + * EP - use expanded packed-decimal format + * AC - use alternate definition for C flag on compare operations + */ + +#define _FPU_RESERVED 0xfff0e0f0 /* These bits are reserved. */ /* The fdlibm code requires no interrupts for exceptions. Don't change the rounding mode, it would break long double I/O! */ @@ -29,11 +76,9 @@ /* Type of the control word. */ typedef unsigned int fpu_control_t; -/* Macros for accessing the hardware control word. - * On the ARM, we can't do this from user mode (it would trap). - */ -#define _FPU_GETCW(cw) __asm__ ("movnv r0,r0" : "=g" (cw)) -#define _FPU_SETCW(cw) __asm__ ("movnv r0,r0" : : "g" (cw)) +/* Macros for accessing the hardware control word. */ +#define _FPU_GETCW(cw) __asm__ ("rfs %0" : "=r" (cw)) +#define _FPU_SETCW(cw) __asm__ ("wfs %0" : : "r" (cw)) /* Default control word set at startup. */ extern fpu_control_t __fpu_control; |