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-rw-r--r--ChangeLog5
-rw-r--r--sysdeps/tile/tilegx/bits/atomic.h10
2 files changed, 14 insertions, 1 deletions
diff --git a/ChangeLog b/ChangeLog
index 1a7d519039..508f5196da 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,8 @@
+2015-01-28  Chris Metcalf  <cmetcalf@ezchip.com>
+
+	* sysdeps/tile/tilegx/bits/atomic.h [!_LP64] (__HAVE_64B_ATOMICS):
+	Define to 0.
+
 2015-01-28  Joseph Myers  <joseph@codesourcery.com>
 
 	* sysdeps/mips/bits/atomic.h [_MIPS_SIM == _ABIN32]
diff --git a/sysdeps/tile/tilegx/bits/atomic.h b/sysdeps/tile/tilegx/bits/atomic.h
index ac654b8946..e75efb1c41 100644
--- a/sysdeps/tile/tilegx/bits/atomic.h
+++ b/sysdeps/tile/tilegx/bits/atomic.h
@@ -21,7 +21,15 @@
 
 #include <arch/spr_def.h>
 
-#define __HAVE_64B_ATOMICS 1
+#ifdef _LP64
+# define __HAVE_64B_ATOMICS 1
+#else
+/* tilegx32 does have 64-bit atomics, but assumptions in the semaphore
+   code mean that unaligned 64-bit atomics will be used if this symbol
+   is true, and unaligned atomics are not supported on tile.  */
+# define __HAVE_64B_ATOMICS 0
+#endif
+
 #define USE_ATOMIC_COMPILER_BUILTINS 0
 
 /* Pick appropriate 8- or 4-byte instruction. */