diff options
30 files changed, 2927 insertions, 2 deletions
diff --git a/ChangeLog b/ChangeLog index aedec5a5a5..bad022e036 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,37 @@ +2015-06-17 Andrew Senkevich <andrew.senkevich@intel.com> + + * bits/libm-simd-decl-stubs.h: Added stubs for log. + * math/bits/mathcalls.h: Added log declaration with __MATHCALL_VEC. + * sysdeps/unix/sysv/linux/x86_64/libmvec.abilist: New versions added. + * sysdeps/x86/fpu/bits/math-vector.h: Added SIMD declaration and asm + redirections for log. + * sysdeps/x86_64/fpu/Makefile (libmvec-support): Added new files. + * sysdeps/x86_64/fpu/Versions: New versions added. + * sysdeps/x86_64/fpu/libm-test-ulps: Regenerated. + * sysdeps/x86_64/fpu/multiarch/Makefile (libmvec-sysdep_routines): Added + build of SSE, AVX2 and AVX512 IFUNC versions. + * sysdeps/x86_64/fpu/multiarch/svml_d_log2_core.S: New file. + * sysdeps/x86_64/fpu/multiarch/svml_d_log2_core_sse4.S: New file. + * sysdeps/x86_64/fpu/multiarch/svml_d_log4_core.S: New file. + * sysdeps/x86_64/fpu/multiarch/svml_d_log4_core_avx2.S: New file. + * sysdeps/x86_64/fpu/multiarch/svml_d_log8_core.S: New file. + * sysdeps/x86_64/fpu/multiarch/svml_d_log8_core_avx512.S: New file. + * sysdeps/x86_64/fpu/svml_d_log2_core.S: New file. + * sysdeps/x86_64/fpu/svml_d_log4_core.S: New file. + * sysdeps/x86_64/fpu/svml_d_log4_core_avx.S: New file. + * sysdeps/x86_64/fpu/svml_d_log8_core.S: New file. + * sysdeps/x86_64/fpu/svml_d_log_data.S: New file. + * sysdeps/x86_64/fpu/svml_d_log_data.h: New file. + * sysdeps/x86_64/fpu/test-double-vlen2-wrappers.c: Added vector log test. + * sysdeps/x86_64/fpu/test-double-vlen2.c: Likewise. + * sysdeps/x86_64/fpu/test-double-vlen4-avx2-wrappers.c: Likewise. + * sysdeps/x86_64/fpu/test-double-vlen4-avx2.c: Likewise. + * sysdeps/x86_64/fpu/test-double-vlen4-wrappers.c: Likewise. + * sysdeps/x86_64/fpu/test-double-vlen4.c: Likewise. + * sysdeps/x86_64/fpu/test-double-vlen8-wrappers.c: Likewise. + * sysdeps/x86_64/fpu/test-double-vlen8.c: Likewise. + * NEWS: Mention addition of x86_64 vector log. + 2015-06-17 Szabolcs Nagy <szabolcs.nagy@arm.com> * sysdeps/aarch64/dl-tlsdesc.S (_dl_tlsdesc_return_lazy): Fix diff --git a/NEWS b/NEWS index b215276b07..4c666878dd 100644 --- a/NEWS +++ b/NEWS @@ -53,7 +53,7 @@ Version 2.22 condition in some applications. * Added vector math library named libmvec with the following vectorized x86_64 - implementations: cos, cosf, sin, sinf. + implementations: cos, cosf, sin, sinf, log. The library can be disabled with --disable-mathvec. Use of the functions is enabled with -fopenmp -ffast-math starting from -O1 for GCC version >= 4.9.0. The library is linked in as needed when using -lm (no need to specify -lmvec diff --git a/bits/libm-simd-decl-stubs.h b/bits/libm-simd-decl-stubs.h index 50310d643a..6367b775a3 100644 --- a/bits/libm-simd-decl-stubs.h +++ b/bits/libm-simd-decl-stubs.h @@ -41,4 +41,8 @@ #define __DECL_SIMD_sinf #define __DECL_SIMD_sinl +#define __DECL_SIMD_log +#define __DECL_SIMD_logf +#define __DECL_SIMD_logl + #endif diff --git a/math/bits/mathcalls.h b/math/bits/mathcalls.h index fbe7a3a6af..c41946fa0e 100644 --- a/math/bits/mathcalls.h +++ b/math/bits/mathcalls.h @@ -106,7 +106,7 @@ __MATHCALL (frexp,, (_Mdouble_ __x, int *__exponent)); __MATHCALL (ldexp,, (_Mdouble_ __x, int __exponent)); /* Natural logarithm of X. */ -__MATHCALL (log,, (_Mdouble_ __x)); +__MATHCALL_VEC (log,, (_Mdouble_ __x)); /* Base-ten logarithm of X. */ __MATHCALL (log10,, (_Mdouble_ __x)); diff --git a/sysdeps/unix/sysv/linux/x86_64/libmvec.abilist b/sysdeps/unix/sysv/linux/x86_64/libmvec.abilist index dcf9c7d148..3357957d3d 100644 --- a/sysdeps/unix/sysv/linux/x86_64/libmvec.abilist +++ b/sysdeps/unix/sysv/linux/x86_64/libmvec.abilist @@ -1,18 +1,22 @@ GLIBC_2.22 GLIBC_2.22 A _ZGVbN2v_cos F + _ZGVbN2v_log F _ZGVbN2v_sin F _ZGVbN4v_cosf F _ZGVbN4v_sinf F _ZGVcN4v_cos F + _ZGVcN4v_log F _ZGVcN4v_sin F _ZGVcN8v_cosf F _ZGVcN8v_sinf F _ZGVdN4v_cos F + _ZGVdN4v_log F _ZGVdN4v_sin F _ZGVdN8v_cosf F _ZGVdN8v_sinf F _ZGVeN16v_cosf F _ZGVeN16v_sinf F _ZGVeN8v_cos F + _ZGVeN8v_log F _ZGVeN8v_sin F diff --git a/sysdeps/x86/fpu/bits/math-vector.h b/sysdeps/x86/fpu/bits/math-vector.h index 2b739c5444..ed85622560 100644 --- a/sysdeps/x86/fpu/bits/math-vector.h +++ b/sysdeps/x86/fpu/bits/math-vector.h @@ -36,5 +36,17 @@ # define __DECL_SIMD_sin __DECL_SIMD_x86_64 # undef __DECL_SIMD_sinf # define __DECL_SIMD_sinf __DECL_SIMD_x86_64 +# undef __DECL_SIMD_log +# define __DECL_SIMD_log __DECL_SIMD_x86_64 + +/* Workaround to exclude unnecessary symbol aliases in libmvec + while GCC creates the vector names based on scalar asm name. + Corresponding discussion started at + <https://gcc.gnu.org/ml/gcc/2015-06/msg00173.html>. */ +__asm__ ("_ZGVbN2v___log_finite = _ZGVbN2v_log"); +__asm__ ("_ZGVcN4v___log_finite = _ZGVcN4v_log"); +__asm__ ("_ZGVdN4v___log_finite = _ZGVdN4v_log"); +__asm__ ("_ZGVeN8v___log_finite = _ZGVeN8v_log"); + # endif #endif diff --git a/sysdeps/x86_64/fpu/Makefile b/sysdeps/x86_64/fpu/Makefile index b6ecbc3cee..a5097468ee 100644 --- a/sysdeps/x86_64/fpu/Makefile +++ b/sysdeps/x86_64/fpu/Makefile @@ -7,6 +7,8 @@ libmvec-support += svml_d_cos2_core svml_d_cos4_core_avx \ svml_s_cosf8_core svml_s_cosf16_core svml_s_cosf_data \ svml_s_sinf4_core svml_s_sinf8_core_avx \ svml_s_sinf8_core svml_s_sinf16_core svml_s_sinf_data \ + svml_d_log2_core svml_d_log4_core_avx svml_d_log4_core \ + svml_d_log8_core svml_d_log_data \ init-arch endif diff --git a/sysdeps/x86_64/fpu/Versions b/sysdeps/x86_64/fpu/Versions index 3f3b22812b..7bda47f4af 100644 --- a/sysdeps/x86_64/fpu/Versions +++ b/sysdeps/x86_64/fpu/Versions @@ -2,6 +2,7 @@ libmvec { GLIBC_2.22 { _ZGVbN2v_cos; _ZGVcN4v_cos; _ZGVdN4v_cos; _ZGVeN8v_cos; _ZGVbN2v_sin; _ZGVcN4v_sin; _ZGVdN4v_sin; _ZGVeN8v_sin; + _ZGVbN2v_log; _ZGVcN4v_log; _ZGVdN4v_log; _ZGVeN8v_log; _ZGVbN4v_cosf; _ZGVcN8v_cosf; _ZGVdN8v_cosf; _ZGVeN16v_cosf; _ZGVbN4v_sinf; _ZGVcN8v_sinf; _ZGVdN8v_sinf; _ZGVeN16v_sinf; } diff --git a/sysdeps/x86_64/fpu/libm-test-ulps b/sysdeps/x86_64/fpu/libm-test-ulps index c2b6c4dfcb..949a099090 100644 --- a/sysdeps/x86_64/fpu/libm-test-ulps +++ b/sysdeps/x86_64/fpu/libm-test-ulps @@ -1847,6 +1847,18 @@ ifloat: 2 ildouble: 1 ldouble: 1 +Function: "log_vlen2": +double: 1 + +Function: "log_vlen4": +double: 1 + +Function: "log_vlen4_avx2": +double: 1 + +Function: "log_vlen8": +double: 1 + Function: "pow": float: 3 ifloat: 3 diff --git a/sysdeps/x86_64/fpu/multiarch/Makefile b/sysdeps/x86_64/fpu/multiarch/Makefile index 61759b8d0b..16d93caf57 100644 --- a/sysdeps/x86_64/fpu/multiarch/Makefile +++ b/sysdeps/x86_64/fpu/multiarch/Makefile @@ -56,6 +56,8 @@ ifeq ($(subdir),mathvec) libmvec-sysdep_routines += svml_d_cos2_core_sse4 svml_d_cos4_core_avx2 \ svml_d_cos8_core_avx512 svml_d_sin2_core_sse4 \ svml_d_sin4_core_avx2 svml_d_sin8_core_avx512 \ + svml_d_log2_core_sse4 svml_d_log4_core_avx2 \ + svml_d_log8_core_avx512 \ svml_s_cosf4_core_sse4 svml_s_cosf8_core_avx2 \ svml_s_cosf16_core_avx512 svml_s_sinf4_core_sse4 \ svml_s_sinf8_core_avx2 svml_s_sinf16_core_avx512 diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_log2_core.S b/sysdeps/x86_64/fpu/multiarch/svml_d_log2_core.S new file mode 100644 index 0000000000..38d369fc3c --- /dev/null +++ b/sysdeps/x86_64/fpu/multiarch/svml_d_log2_core.S @@ -0,0 +1,38 @@ +/* Multiple versions of vectorized log. + Copyright (C) 2014-2015 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVbN2v_log) + .type _ZGVbN2v_log, @gnu_indirect_function + cmpl $0, KIND_OFFSET+__cpu_features(%rip) + jne 1f + call __init_cpu_features +1: leaq _ZGVbN2v_log_sse4(%rip), %rax + testl $bit_SSE4_1, __cpu_features+CPUID_OFFSET+index_SSE4_1(%rip) + jz 2f + ret +2: leaq _ZGVbN2v_log_sse2(%rip), %rax + ret +END (_ZGVbN2v_log) +libmvec_hidden_def (_ZGVbN2v_log) + +#define _ZGVbN2v_log _ZGVbN2v_log_sse2 +#include "../svml_d_log2_core.S" diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_log2_core_sse4.S b/sysdeps/x86_64/fpu/multiarch/svml_d_log2_core_sse4.S new file mode 100644 index 0000000000..82f3d8215d --- /dev/null +++ b/sysdeps/x86_64/fpu/multiarch/svml_d_log2_core_sse4.S @@ -0,0 +1,229 @@ +/* Function log vectorized with SSE4. + Copyright (C) 2014-2015 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_log_data.h" + + .text +ENTRY (_ZGVbN2v_log_sse4) +/* + ALGORITHM DESCRIPTION: + + log(x) = -log(Rcp) + log(Rcp*x), + where Rcp ~ 1/x (accuracy ~9 bits, obtained by rounding + HW approximation to 1+9 mantissa bits) + + Reduced argument R=Rcp*x-1 is used to approximate log(1+R) as polynomial + + log(Rcp) = exponent_Rcp*log(2) + log(mantissa_Rcp) + -log(mantissa_Rcp) is obtained from a lookup table, + accessed by a 9-bit index + */ + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $320, %rsp + movaps %xmm0, %xmm6 + movq __svml_dlog_data@GOTPCREL(%rip), %r8 + movaps %xmm6, %xmm3 + movaps %xmm6, %xmm2 + +/* isolate exponent bits */ + movaps %xmm6, %xmm1 + psrlq $20, %xmm1 + movups _ExpMask(%r8), %xmm5 + +/* preserve mantissa, set input exponent to 2^(-10) */ + andps %xmm6, %xmm5 + orps _Two10(%r8), %xmm5 + +/* reciprocal approximation good to at least 11 bits */ + cvtpd2ps %xmm5, %xmm7 + cmpltpd _MinNorm(%r8), %xmm3 + cmpnlepd _MaxNorm(%r8), %xmm2 + movlhps %xmm7, %xmm7 + +/* combine and get argument value range mask */ + orps %xmm2, %xmm3 + rcpps %xmm7, %xmm0 + movmskpd %xmm3, %eax + movups _HalfMask(%r8), %xmm2 + +/* argument reduction started: R = Mantissa*Rcp - 1 */ + andps %xmm5, %xmm2 + cvtps2pd %xmm0, %xmm4 + subpd %xmm2, %xmm5 + +/* round reciprocal to nearest integer, will have 1+9 mantissa bits */ + roundpd $0, %xmm4, %xmm4 + mulpd %xmm4, %xmm2 + mulpd %xmm4, %xmm5 + subpd _One(%r8), %xmm2 + addpd %xmm2, %xmm5 + movups _Threshold(%r8), %xmm2 + +/* calculate index for table lookup */ + movaps %xmm4, %xmm3 + cmpltpd %xmm4, %xmm2 + pshufd $221, %xmm1, %xmm7 + psrlq $40, %xmm3 + +/* convert biased exponent to DP format */ + cvtdq2pd %xmm7, %xmm0 + movd %xmm3, %edx + movups _poly_coeff_1(%r8), %xmm4 + +/* polynomial computation */ + mulpd %xmm5, %xmm4 + andps _Bias(%r8), %xmm2 + orps _Bias1(%r8), %xmm2 + +/* + Table stores -log(0.5*mantissa) for larger mantissas, + adjust exponent accordingly + */ + subpd %xmm2, %xmm0 + addpd _poly_coeff_2(%r8), %xmm4 + +/* exponent*log(2.0) */ + mulpd _L2(%r8), %xmm0 + movaps %xmm5, %xmm2 + mulpd %xmm5, %xmm2 + movups _poly_coeff_3(%r8), %xmm7 + mulpd %xmm5, %xmm7 + mulpd %xmm2, %xmm4 + addpd _poly_coeff_4(%r8), %xmm7 + addpd %xmm4, %xmm7 + mulpd %xmm7, %xmm2 + movslq %edx, %rdx + pextrd $2, %xmm3, %ecx + +/* + reconstruction: + (exponent*log(2)) + (LogRcp + (R+poly)) + */ + addpd %xmm2, %xmm5 + movslq %ecx, %rcx + movsd _LogRcp_lookup(%r8,%rdx), %xmm1 + movhpd _LogRcp_lookup(%r8,%rcx), %xmm1 + addpd %xmm5, %xmm1 + addpd %xmm1, %xmm0 + testl %eax, %eax + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + movups %xmm6, 192(%rsp) + movups %xmm0, 256(%rsp) + je .LBL_1_2 + + xorb %cl, %cl + xorl %edx, %edx + movups %xmm8, 112(%rsp) + movups %xmm9, 96(%rsp) + movups %xmm10, 80(%rsp) + movups %xmm11, 64(%rsp) + movups %xmm12, 48(%rsp) + movups %xmm13, 32(%rsp) + movups %xmm14, 16(%rsp) + movups %xmm15, (%rsp) + movq %rsi, 136(%rsp) + movq %rdi, 128(%rsp) + movq %r12, 168(%rsp) + cfi_offset_rel_rsp (12, 168) + movb %cl, %r12b + movq %r13, 160(%rsp) + cfi_offset_rel_rsp (13, 160) + movl %eax, %r13d + movq %r14, 152(%rsp) + cfi_offset_rel_rsp (14, 152) + movl %edx, %r14d + movq %r15, 144(%rsp) + cfi_offset_rel_rsp (15, 144) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + movups 112(%rsp), %xmm8 + movups 96(%rsp), %xmm9 + movups 80(%rsp), %xmm10 + movups 64(%rsp), %xmm11 + movups 48(%rsp), %xmm12 + movups 32(%rsp), %xmm13 + movups 16(%rsp), %xmm14 + movups (%rsp), %xmm15 + movq 136(%rsp), %rsi + movq 128(%rsp), %rdi + movq 168(%rsp), %r12 + cfi_restore (%r12) + movq 160(%rsp), %r13 + cfi_restore (%r13) + movq 152(%rsp), %r14 + cfi_restore (%r14) + movq 144(%rsp), %r15 + cfi_restore (%r15) + movups 256(%rsp), %xmm0 + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + shlq $4, %r15 + movsd 200(%rsp,%r15), %xmm0 + + call log@PLT + + movsd %xmm0, 264(%rsp,%r15) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + shlq $4, %r15 + movsd 192(%rsp,%r15), %xmm0 + + call log@PLT + + movsd %xmm0, 256(%rsp,%r15) + jmp .LBL_1_7 + +END (_ZGVbN2v_log_sse4) diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_log4_core.S b/sysdeps/x86_64/fpu/multiarch/svml_d_log4_core.S new file mode 100644 index 0000000000..ddb6105405 --- /dev/null +++ b/sysdeps/x86_64/fpu/multiarch/svml_d_log4_core.S @@ -0,0 +1,38 @@ +/* Multiple versions of vectorized log. + Copyright (C) 2014-2015 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVdN4v_log) + .type _ZGVdN4v_log, @gnu_indirect_function + cmpl $0, KIND_OFFSET+__cpu_features(%rip) + jne 1f + call __init_cpu_features +1: leaq _ZGVdN4v_log_avx2(%rip), %rax + testl $bit_AVX2_Usable, __cpu_features+FEATURE_OFFSET+index_AVX2_Usable(%rip) + jz 2f + ret +2: leaq _ZGVdN4v_log_sse_wrapper(%rip), %rax + ret +END (_ZGVdN4v_log) +libmvec_hidden_def (_ZGVdN4v_log) + +#define _ZGVdN4v_log _ZGVdN4v_log_sse_wrapper +#include "../svml_d_log4_core.S" diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_log4_core_avx2.S b/sysdeps/x86_64/fpu/multiarch/svml_d_log4_core_avx2.S new file mode 100644 index 0000000000..816aede395 --- /dev/null +++ b/sysdeps/x86_64/fpu/multiarch/svml_d_log4_core_avx2.S @@ -0,0 +1,210 @@ +/* Function log vectorized with AVX2. + Copyright (C) 2014-2015 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_log_data.h" + + .text +ENTRY (_ZGVdN4v_log_avx2) +/* ALGORITHM DESCRIPTION: + + log(x) = -log(Rcp) + log(Rcp*x), + where Rcp ~ 1/x (accuracy ~9 bits, obtained by rounding + HW approximation to 1+9 mantissa bits) + + Reduced argument R=Rcp*x-1 is used to approximate log(1+R) as polynomial + + log(Rcp) = exponent_Rcp*log(2) + log(mantissa_Rcp) + -log(mantissa_Rcp) is obtained from a lookup table, + accessed by a 9-bit index + */ + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $448, %rsp + movq __svml_dlog_data@GOTPCREL(%rip), %rax + vmovdqa %ymm0, %ymm5 + +/* isolate exponent bits */ + vpsrlq $20, %ymm5, %ymm0 + +/* preserve mantissa, set input exponent to 2^(-10) */ + vandpd _ExpMask(%rax), %ymm5, %ymm6 + vorpd _Two10(%rax), %ymm6, %ymm4 + +/* reciprocal approximation good to at least 11 bits */ + vcvtpd2ps %ymm4, %xmm7 + vrcpps %xmm7, %xmm1 + vcmplt_oqpd _MinNorm(%rax), %ymm5, %ymm7 + vcvtps2pd %xmm1, %ymm3 + vcmpnle_uqpd _MaxNorm(%rax), %ymm5, %ymm1 + vextracti128 $1, %ymm0, %xmm2 + vshufps $221, %xmm2, %xmm0, %xmm6 + +/* round reciprocal to nearest integer, will have 1+9 mantissa bits */ + vroundpd $0, %ymm3, %ymm2 + +/* convert biased exponent to DP format */ + vcvtdq2pd %xmm6, %ymm0 + +/* combine and get argument value range mask */ + vorpd %ymm1, %ymm7, %ymm3 + vmovupd _One(%rax), %ymm1 + vmovmskpd %ymm3, %ecx + +/* calculate index for table lookup */ + vpsrlq $40, %ymm2, %ymm3 + +/* argument reduction started: R = Mantissa*Rcp - 1 */ + vfmsub213pd %ymm1, %ymm2, %ymm4 + vcmpgt_oqpd _Threshold(%rax), %ymm2, %ymm2 + vpcmpeqd %ymm6, %ymm6, %ymm6 + vxorpd %ymm1, %ymm1, %ymm1 + vgatherqpd %ymm6, _LogRcp_lookup(%rax,%ymm3), %ymm1 + +/* exponent*log(2.0) */ + vmovupd _poly_coeff_1(%rax), %ymm6 + vmulpd %ymm4, %ymm4, %ymm3 + +/* polynomial computation */ + vfmadd213pd _poly_coeff_2(%rax), %ymm4, %ymm6 + vandpd _Bias(%rax), %ymm2, %ymm7 + vorpd _Bias1(%rax), %ymm7, %ymm2 + +/* + Table stores -log(0.5*mantissa) for larger mantissas, + adjust exponent accordingly + */ + vsubpd %ymm2, %ymm0, %ymm0 + vmovupd _poly_coeff_3(%rax), %ymm2 + vfmadd213pd _poly_coeff_4(%rax), %ymm4, %ymm2 + vfmadd213pd %ymm2, %ymm3, %ymm6 + +/* + reconstruction: + (exponent*log(2)) + (LogRcp + (R+poly)) + */ + vfmadd213pd %ymm4, %ymm3, %ymm6 + vaddpd %ymm1, %ymm6, %ymm4 + vfmadd132pd _L2(%rax), %ymm4, %ymm0 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + vmovupd %ymm5, 320(%rsp) + vmovupd %ymm0, 384(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + xorl %eax, %eax + vmovups %ymm8, 224(%rsp) + vmovups %ymm9, 192(%rsp) + vmovups %ymm10, 160(%rsp) + vmovups %ymm11, 128(%rsp) + vmovups %ymm12, 96(%rsp) + vmovups %ymm13, 64(%rsp) + vmovups %ymm14, 32(%rsp) + vmovups %ymm15, (%rsp) + movq %rsi, 264(%rsp) + movq %rdi, 256(%rsp) + movq %r12, 296(%rsp) + cfi_offset_rel_rsp (12, 296) + movb %dl, %r12b + movq %r13, 288(%rsp) + cfi_offset_rel_rsp (13, 288) + movl %ecx, %r13d + movq %r14, 280(%rsp) + cfi_offset_rel_rsp (14, 280) + movl %eax, %r14d + movq %r15, 272(%rsp) + cfi_offset_rel_rsp (15, 272) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + vmovups 224(%rsp), %ymm8 + vmovups 192(%rsp), %ymm9 + vmovups 160(%rsp), %ymm10 + vmovups 128(%rsp), %ymm11 + vmovups 96(%rsp), %ymm12 + vmovups 64(%rsp), %ymm13 + vmovups 32(%rsp), %ymm14 + vmovups (%rsp), %ymm15 + vmovupd 384(%rsp), %ymm0 + movq 264(%rsp), %rsi + movq 256(%rsp), %rdi + movq 296(%rsp), %r12 + cfi_restore (%r12) + movq 288(%rsp), %r13 + cfi_restore (%r13) + movq 280(%rsp), %r14 + cfi_restore (%r14) + movq 272(%rsp), %r15 + cfi_restore (%r15) + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 328(%rsp,%r15), %xmm0 + vzeroupper + + call log@PLT + + vmovsd %xmm0, 392(%rsp,%r15) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 320(%rsp,%r15), %xmm0 + vzeroupper + + call log@PLT + + vmovsd %xmm0, 384(%rsp,%r15) + jmp .LBL_1_7 + +END (_ZGVdN4v_log_avx2) diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_log8_core.S b/sysdeps/x86_64/fpu/multiarch/svml_d_log8_core.S new file mode 100644 index 0000000000..2f9e9d8892 --- /dev/null +++ b/sysdeps/x86_64/fpu/multiarch/svml_d_log8_core.S @@ -0,0 +1,39 @@ +/* Multiple versions of vectorized log. + Copyright (C) 2014-2015 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVeN8v_log) + .type _ZGVeN8v_log, @gnu_indirect_function + cmpl $0, KIND_OFFSET+__cpu_features(%rip) + jne 1 + call __init_cpu_features +1: leaq _ZGVeN8v_log_skx(%rip), %rax + testl $bit_AVX512DQ_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512DQ_Usable(%rip) + jnz 3 +2: leaq _ZGVeN8v_log_knl(%rip), %rax + testl $bit_AVX512F_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512F_Usable(%rip) + jnz 3 + leaq _ZGVeN8v_log_avx2_wrapper(%rip), %rax +3: ret +END (_ZGVeN8v_log) + +#define _ZGVeN8v_log _ZGVeN8v_log_avx2_wrapper +#include "../svml_d_log8_core.S" diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_log8_core_avx512.S b/sysdeps/x86_64/fpu/multiarch/svml_d_log8_core_avx512.S new file mode 100644 index 0000000000..b0f3dd580c --- /dev/null +++ b/sysdeps/x86_64/fpu/multiarch/svml_d_log8_core_avx512.S @@ -0,0 +1,468 @@ +/* Function log vectorized with AVX-512. KNL and SKX versions. + Copyright (C) 2014-2015 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_log_data.h" +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVeN8v_log_knl) +#ifndef HAVE_AVX512_ASM_SUPPORT +WRAPPER_IMPL_AVX512 _ZGVdN4v_log +#else +/* + ALGORITHM DESCRIPTION: + + log(x) = -log(Rcp) + log(Rcp*x), + where Rcp ~ 1/x (accuracy ~9 bits, obtained by + rounding HW approximation to 1+9 mantissa bits) + + Reduced argument R=Rcp*x-1 is used to approximate log(1+R) as polynomial + + log(Rcp) = exponent_Rcp*log(2) + log(mantissa_Rcp) + -log(mantissa_Rcp) is obtained from a lookup table, + accessed by a 9-bit index + */ + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $1280, %rsp + movq __svml_dlog_data@GOTPCREL(%rip), %rdx + movq $-1, %rax + +/* isolate exponent bits */ + vpsrlq $20, %zmm0, %zmm2 + vpsrlq $32, %zmm2, %zmm3 + vpxord %zmm2, %zmm2, %zmm2 + kxnorw %k3, %k3, %k3 + vmovups _Two10(%rdx), %zmm1 + vmovups _One(%rdx), %zmm9 + vpmovqd %zmm3, %ymm4 + +/* convert biased exponent to DP format */ + vcvtdq2pd %ymm4, %zmm13 + +/* preserve mantissa, set input exponent to 2^(-10) */ + vpternlogq $248, _ExpMask(%rdx), %zmm0, %zmm1 + vcmppd $17, _MinNorm(%rdx), %zmm0, %k1 + +/* reciprocal approximation good to at least 11 bits */ + vrcp28pd %zmm1, %zmm5 + vpbroadcastq %rax, %zmm6{%k1}{z} + vmovups _poly_coeff_3(%rdx), %zmm15 + vcmppd $22, _MaxNorm(%rdx), %zmm0, %k2 + vmovups _Bias1(%rdx), %zmm14 + +/* round reciprocal to nearest integer, will have 1+9 mantissa bits */ + vrndscalepd $8, %zmm5, %zmm11 + vpbroadcastq %rax, %zmm7{%k2}{z} + +/* argument reduction started: R = Mantissa*Rcp - 1 */ + vfmsub213pd %zmm9, %zmm11, %zmm1 + +/* calculate index for table lookup */ + vpsrlq $40, %zmm11, %zmm10 + vgatherqpd _LogRcp_lookup(%rdx,%zmm10), %zmm2{%k3} + vcmppd $30, _Threshold(%rdx), %zmm11, %k1 + +/* combine and get argument value range mask */ + vporq %zmm7, %zmm6, %zmm8 + +/* exponent*log(2.0) */ + vmovups _poly_coeff_1(%rdx), %zmm11 + vmulpd %zmm1, %zmm1, %zmm10 + vptestmq %zmm8, %zmm8, %k0 + vfmadd213pd _poly_coeff_4(%rdx), %zmm1, %zmm15 + kmovw %k0, %ecx + +/* polynomial computation */ + vfmadd213pd _poly_coeff_2(%rdx), %zmm1, %zmm11 + movzbl %cl, %ecx + vpbroadcastq %rax, %zmm12{%k1}{z} + vfmadd213pd %zmm15, %zmm10, %zmm11 + vpternlogq $248, _Bias(%rdx), %zmm12, %zmm14 + +/* + Table stores -log(0.5*mantissa) for larger mantissas, + adjust exponent accordingly + */ + vsubpd %zmm14, %zmm13, %zmm3 + +/* + reconstruction: + (exponent*log(2)) + (LogRcp + (R+poly)) + */ + vfmadd213pd %zmm1, %zmm10, %zmm11 + vaddpd %zmm2, %zmm11, %zmm1 + vfmadd132pd _L2(%rdx), %zmm1, %zmm3 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + vmovaps %zmm3, %zmm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + vmovups %zmm0, 1152(%rsp) + vmovups %zmm3, 1216(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + kmovw %k4, 1048(%rsp) + xorl %eax, %eax + kmovw %k5, 1040(%rsp) + kmovw %k6, 1032(%rsp) + kmovw %k7, 1024(%rsp) + vmovups %zmm16, 960(%rsp) + vmovups %zmm17, 896(%rsp) + vmovups %zmm18, 832(%rsp) + vmovups %zmm19, 768(%rsp) + vmovups %zmm20, 704(%rsp) + vmovups %zmm21, 640(%rsp) + vmovups %zmm22, 576(%rsp) + vmovups %zmm23, 512(%rsp) + vmovups %zmm24, 448(%rsp) + vmovups %zmm25, 384(%rsp) + vmovups %zmm26, 320(%rsp) + vmovups %zmm27, 256(%rsp) + vmovups %zmm28, 192(%rsp) + vmovups %zmm29, 128(%rsp) + vmovups %zmm30, 64(%rsp) + vmovups %zmm31, (%rsp) + movq %rsi, 1064(%rsp) + movq %rdi, 1056(%rsp) + movq %r12, 1096(%rsp) + cfi_offset_rel_rsp (12, 1096) + movb %dl, %r12b + movq %r13, 1088(%rsp) + cfi_offset_rel_rsp (13, 1088) + movl %ecx, %r13d + movq %r14, 1080(%rsp) + cfi_offset_rel_rsp (14, 1080) + movl %eax, %r14d + movq %r15, 1072(%rsp) + cfi_offset_rel_rsp (15, 1072) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + addb $1, %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + kmovw 1048(%rsp), %k4 + movq 1064(%rsp), %rsi + kmovw 1040(%rsp), %k5 + movq 1056(%rsp), %rdi + kmovw 1032(%rsp), %k6 + movq 1096(%rsp), %r12 + cfi_restore (%r12) + movq 1088(%rsp), %r13 + cfi_restore (%r13) + kmovw 1024(%rsp), %k7 + vmovups 960(%rsp), %zmm16 + vmovups 896(%rsp), %zmm17 + vmovups 832(%rsp), %zmm18 + vmovups 768(%rsp), %zmm19 + vmovups 704(%rsp), %zmm20 + vmovups 640(%rsp), %zmm21 + vmovups 576(%rsp), %zmm22 + vmovups 512(%rsp), %zmm23 + vmovups 448(%rsp), %zmm24 + vmovups 384(%rsp), %zmm25 + vmovups 320(%rsp), %zmm26 + vmovups 256(%rsp), %zmm27 + vmovups 192(%rsp), %zmm28 + vmovups 128(%rsp), %zmm29 + vmovups 64(%rsp), %zmm30 + vmovups (%rsp), %zmm31 + movq 1080(%rsp), %r14 + cfi_restore (%r14) + movq 1072(%rsp), %r15 + cfi_restore (%r15) + vmovups 1216(%rsp), %zmm3 + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 1160(%rsp,%r15), %xmm0 + call log@PLT + vmovsd %xmm0, 1224(%rsp,%r15) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 1152(%rsp,%r15), %xmm0 + call log@PLT + vmovsd %xmm0, 1216(%rsp,%r15) + jmp .LBL_1_7 +#endif +END (_ZGVeN8v_log_knl) + +ENTRY (_ZGVeN8v_log_skx) +#ifndef HAVE_AVX512_ASM_SUPPORT +WRAPPER_IMPL_AVX512 _ZGVdN4v_log +#else +/* + ALGORITHM DESCRIPTION: + + log(x) = -log(Rcp) + log(Rcp*x), + where Rcp ~ 1/x (accuracy ~9 bits, + obtained by rounding HW approximation to 1+9 mantissa bits) + + Reduced argument R=Rcp*x-1 is used to approximate log(1+R) as polynomial + + log(Rcp) = exponent_Rcp*log(2) + log(mantissa_Rcp) + -log(mantissa_Rcp) is obtained from a lookup table, + accessed by a 9-bit index + */ + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $1280, %rsp + movq __svml_dlog_data@GOTPCREL(%rip), %rax + vmovaps %zmm0, %zmm3 + kxnorw %k3, %k3, %k3 + vmovups _Two10(%rax), %zmm2 + vmovups _Threshold(%rax), %zmm14 + vmovups _One(%rax), %zmm11 + vcmppd $21, _MinNorm(%rax), %zmm3, %k1 + vcmppd $18, _MaxNorm(%rax), %zmm3, %k2 + +/* isolate exponent bits */ + vpsrlq $20, %zmm3, %zmm4 + +/* preserve mantissa, set input exponent to 2^(-10) */ + vpternlogq $248, _ExpMask(%rax), %zmm3, %zmm2 + vpbroadcastq .L_2il0floatpacket.12(%rip), %zmm1 + vpsrlq $32, %zmm4, %zmm6 + +/* reciprocal approximation good to at least 11 bits */ + vrcp14pd %zmm2, %zmm5 + +/* exponent*log(2.0) */ + vmovups _poly_coeff_1(%rax), %zmm4 + vpmovqd %zmm6, %ymm7 + +/* round reciprocal to nearest integer, will have 1+9 mantissa bits */ + vrndscalepd $8, %zmm5, %zmm0 + +/* calculate index for table lookup */ + vpsrlq $40, %zmm0, %zmm12 + +/* argument reduction started: R = Mantissa*Rcp - 1 */ + vfmsub213pd %zmm11, %zmm0, %zmm2 + vpmovqd %zmm12, %ymm13 + +/* polynomial computation */ + vfmadd213pd _poly_coeff_2(%rax), %zmm2, %zmm4 + vmovaps %zmm1, %zmm8 + vmovaps %zmm1, %zmm9 + vpxord %zmm5, %zmm5, %zmm5 + vgatherdpd _LogRcp_lookup(%rax,%ymm13), %zmm5{%k3} + vmovups _Bias1(%rax), %zmm13 + vpandnq %zmm3, %zmm3, %zmm8{%k1} + vcmppd $21, %zmm0, %zmm14, %k1 + vpandnq %zmm14, %zmm14, %zmm1{%k1} + vmulpd %zmm2, %zmm2, %zmm14 + vpternlogq $248, _Bias(%rax), %zmm1, %zmm13 + vmovups _poly_coeff_3(%rax), %zmm1 + vfmadd213pd _poly_coeff_4(%rax), %zmm2, %zmm1 + vfmadd213pd %zmm1, %zmm14, %zmm4 + +/* + reconstruction: + (exponent*log(2)) + (LogRcp + (R+poly)) + */ + vfmadd213pd %zmm2, %zmm14, %zmm4 + vaddpd %zmm5, %zmm4, %zmm2 + vpandnq %zmm3, %zmm3, %zmm9{%k2} + +/* combine and get argument value range mask */ + vorpd %zmm9, %zmm8, %zmm10 + vcmppd $3, %zmm10, %zmm10, %k0 + kmovw %k0, %ecx + +/* convert biased exponent to DP format */ + vcvtdq2pd %ymm7, %zmm15 + +/* + Table stores -log(0.5*mantissa) for larger mantissas, + adjust exponent accordingly + */ + vsubpd %zmm13, %zmm15, %zmm0 + vfmadd132pd _L2(%rax), %zmm2, %zmm0 + testl %ecx, %ecx + jne .LBL_2_3 + +.LBL_2_2: + cfi_remember_state + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_2_3: + cfi_restore_state + vmovups %zmm3, 1152(%rsp) + vmovups %zmm0, 1216(%rsp) + je .LBL_2_2 + + xorb %dl, %dl + xorl %eax, %eax + kmovw %k4, 1048(%rsp) + kmovw %k5, 1040(%rsp) + kmovw %k6, 1032(%rsp) + kmovw %k7, 1024(%rsp) + vmovups %zmm16, 960(%rsp) + vmovups %zmm17, 896(%rsp) + vmovups %zmm18, 832(%rsp) + vmovups %zmm19, 768(%rsp) + vmovups %zmm20, 704(%rsp) + vmovups %zmm21, 640(%rsp) + vmovups %zmm22, 576(%rsp) + vmovups %zmm23, 512(%rsp) + vmovups %zmm24, 448(%rsp) + vmovups %zmm25, 384(%rsp) + vmovups %zmm26, 320(%rsp) + vmovups %zmm27, 256(%rsp) + vmovups %zmm28, 192(%rsp) + vmovups %zmm29, 128(%rsp) + vmovups %zmm30, 64(%rsp) + vmovups %zmm31, (%rsp) + movq %rsi, 1064(%rsp) + movq %rdi, 1056(%rsp) + movq %r12, 1096(%rsp) + cfi_offset_rel_rsp (12, 1096) + movb %dl, %r12b + movq %r13, 1088(%rsp) + cfi_offset_rel_rsp (13, 1088) + movl %ecx, %r13d + movq %r14, 1080(%rsp) + cfi_offset_rel_rsp (14, 1080) + movl %eax, %r14d + movq %r15, 1072(%rsp) + cfi_offset_rel_rsp (15, 1072) + cfi_remember_state + +.LBL_2_6: + btl %r14d, %r13d + jc .LBL_2_12 + +.LBL_2_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_2_10 + +.LBL_2_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_2_6 + + kmovw 1048(%rsp), %k4 + kmovw 1040(%rsp), %k5 + kmovw 1032(%rsp), %k6 + kmovw 1024(%rsp), %k7 + vmovups 960(%rsp), %zmm16 + vmovups 896(%rsp), %zmm17 + vmovups 832(%rsp), %zmm18 + vmovups 768(%rsp), %zmm19 + vmovups 704(%rsp), %zmm20 + vmovups 640(%rsp), %zmm21 + vmovups 576(%rsp), %zmm22 + vmovups 512(%rsp), %zmm23 + vmovups 448(%rsp), %zmm24 + vmovups 384(%rsp), %zmm25 + vmovups 320(%rsp), %zmm26 + vmovups 256(%rsp), %zmm27 + vmovups 192(%rsp), %zmm28 + vmovups 128(%rsp), %zmm29 + vmovups 64(%rsp), %zmm30 + vmovups (%rsp), %zmm31 + vmovups 1216(%rsp), %zmm0 + movq 1064(%rsp), %rsi + movq 1056(%rsp), %rdi + movq 1096(%rsp), %r12 + cfi_restore (%r12) + movq 1088(%rsp), %r13 + cfi_restore (%r13) + movq 1080(%rsp), %r14 + cfi_restore (%r14) + movq 1072(%rsp), %r15 + cfi_restore (%r15) + jmp .LBL_2_2 + +.LBL_2_10: + cfi_restore_state + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 1160(%rsp,%r15), %xmm0 + vzeroupper + vmovsd 1160(%rsp,%r15), %xmm0 + + call log@PLT + + vmovsd %xmm0, 1224(%rsp,%r15) + jmp .LBL_2_8 + +.LBL_2_12: + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 1152(%rsp,%r15), %xmm0 + vzeroupper + vmovsd 1152(%rsp,%r15), %xmm0 + + call log@PLT + + vmovsd %xmm0, 1216(%rsp,%r15) + jmp .LBL_2_7 +#endif +END (_ZGVeN8v_log_skx) + + .section .rodata, "a" +.L_2il0floatpacket.12: + .long 0xffffffff,0xffffffff + .type .L_2il0floatpacket.12,@object diff --git a/sysdeps/x86_64/fpu/svml_d_log2_core.S b/sysdeps/x86_64/fpu/svml_d_log2_core.S new file mode 100644 index 0000000000..daa63b583f --- /dev/null +++ b/sysdeps/x86_64/fpu/svml_d_log2_core.S @@ -0,0 +1,29 @@ +/* Function log vectorized with SSE2. + Copyright (C) 2014-2015 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVbN2v_log) +WRAPPER_IMPL_SSE2 log +END (_ZGVbN2v_log) + +#ifndef USE_MULTIARCH + libmvec_hidden_def (_ZGVbN2v_log) +#endif diff --git a/sysdeps/x86_64/fpu/svml_d_log4_core.S b/sysdeps/x86_64/fpu/svml_d_log4_core.S new file mode 100644 index 0000000000..009c93c837 --- /dev/null +++ b/sysdeps/x86_64/fpu/svml_d_log4_core.S @@ -0,0 +1,29 @@ +/* Function log vectorized with AVX2, wrapper version. + Copyright (C) 2014-2015 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVdN4v_log) +WRAPPER_IMPL_AVX _ZGVbN2v_log +END (_ZGVdN4v_log) + +#ifndef USE_MULTIARCH + libmvec_hidden_def (_ZGVdN4v_log) +#endif diff --git a/sysdeps/x86_64/fpu/svml_d_log4_core_avx.S b/sysdeps/x86_64/fpu/svml_d_log4_core_avx.S new file mode 100644 index 0000000000..554fc45712 --- /dev/null +++ b/sysdeps/x86_64/fpu/svml_d_log4_core_avx.S @@ -0,0 +1,25 @@ +/* Function log vectorized in AVX ISA as wrapper to SSE4 ISA version. + Copyright (C) 2014-2015 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVcN4v_log) +WRAPPER_IMPL_AVX _ZGVbN2v_log +END (_ZGVcN4v_log) diff --git a/sysdeps/x86_64/fpu/svml_d_log8_core.S b/sysdeps/x86_64/fpu/svml_d_log8_core.S new file mode 100644 index 0000000000..9728305f17 --- /dev/null +++ b/sysdeps/x86_64/fpu/svml_d_log8_core.S @@ -0,0 +1,25 @@ +/* Function log vectorized with AVX-512. Wrapper to AVX2 version. + Copyright (C) 2014-2015 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVeN8v_log) +WRAPPER_IMPL_AVX512 _ZGVdN4v_log +END (_ZGVeN8v_log) diff --git a/sysdeps/x86_64/fpu/svml_d_log_data.S b/sysdeps/x86_64/fpu/svml_d_log_data.S new file mode 100644 index 0000000000..1ce78e2c8b --- /dev/null +++ b/sysdeps/x86_64/fpu/svml_d_log_data.S @@ -0,0 +1,1662 @@ +/* Data for function log. + Copyright (C) 2014-2015 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "svml_d_log_data.h" + + .section .rodata, "a" + .align 64 + +/* Data table for vector implementations of function log. + The table may contain polynomial, reduction, lookup coefficients + and other constants obtained through different methods + of research and experimental work. */ + .globl __svml_dlog_data +__svml_dlog_data: + +/* Lookup table in high+low parts and 9-bit index for + -log(mRcp), where mRcp is mantissa of 1/x 9-bit accurate reciprocal: */ +.if .-__svml_dlog_data != _Log_HA_table +.err +.endif + .quad 0xc086232bdd7a8300 + .quad 0xbe1ce91eef3fb100 + .quad 0xc086232fdc7ad828 + .quad 0xbe1cefcffda73b6a + .quad 0xc0862333d97d2ba0 + .quad 0xbe1cef406748f1ff + .quad 0xc0862337d48378e0 + .quad 0xbe1cef2a9429925a + .quad 0xc086233bcd8fb878 + .quad 0xbe1cf138d17ebecb + .quad 0xc086233fc4a3e018 + .quad 0xbe1ceff2dbbbb29e + .quad 0xc0862343b9c1e270 + .quad 0xbe1cf1a42aae437b + .quad 0xc0862347acebaf68 + .quad 0xbe1cef3b152048af + .quad 0xc086234b9e2333f0 + .quad 0xbe1cef20e127805e + .quad 0xc086234f8d6a5a30 + .quad 0xbe1cf00ad6052cf4 + .quad 0xc08623537ac30980 + .quad 0xbe1cefc4642ee597 + .quad 0xc0862357662f2660 + .quad 0xbe1cf1f277d36e16 + .quad 0xc086235b4fb092a0 + .quad 0xbe1ceed009e8d8e6 + .quad 0xc086235f37492d28 + .quad 0xbe1cf1e4038cb362 + .quad 0xc08623631cfad250 + .quad 0xbe1cf0b0873b8557 + .quad 0xc086236700c75b98 + .quad 0xbe1cf15bb3227c0b + .quad 0xc086236ae2b09fe0 + .quad 0xbe1cf151ef8ca9ed + .quad 0xc086236ec2b87358 + .quad 0xbe1cefe1dc2cd2ed + .quad 0xc0862372a0e0a780 + .quad 0xbe1cf0d1eec5454f + .quad 0xc08623767d2b0b48 + .quad 0xbe1ceeefd570bbce + .quad 0xc086237a57996af0 + .quad 0xbe1cee99ae91b3a7 + .quad 0xc086237e302d9028 + .quad 0xbe1cf0412830fbd1 + .quad 0xc086238206e94218 + .quad 0xbe1ceee898588610 + .quad 0xc0862385dbce4548 + .quad 0xbe1cee9a1fbcaaea + .quad 0xc0862389aede5bc0 + .quad 0xbe1ceed8e7cc1ad6 + .quad 0xc086238d801b4500 + .quad 0xbe1cf10c8d059da6 + .quad 0xc08623914f86be18 + .quad 0xbe1ceee6c63a8165 + .quad 0xc08623951d228180 + .quad 0xbe1cf0c3592d2ff1 + .quad 0xc0862398e8f04758 + .quad 0xbe1cf0026cc4cb1b + .quad 0xc086239cb2f1c538 + .quad 0xbe1cf15d48d8e670 + .quad 0xc08623a07b28ae60 + .quad 0xbe1cef359363787c + .quad 0xc08623a44196b390 + .quad 0xbe1cefdf1ab2e82c + .quad 0xc08623a8063d8338 + .quad 0xbe1cefe43c02aa84 + .quad 0xc08623abc91ec960 + .quad 0xbe1cf044f5ae35b7 + .quad 0xc08623af8a3c2fb8 + .quad 0xbe1cf0b0b4001e1b + .quad 0xc08623b349975d98 + .quad 0xbe1cf1bae76dfbcf + .quad 0xc08623b70731f810 + .quad 0xbe1cef0a72e13a62 + .quad 0xc08623bac30da1c8 + .quad 0xbe1cf184007d2b6b + .quad 0xc08623be7d2bfb40 + .quad 0xbe1cf16f4b239e98 + .quad 0xc08623c2358ea2a0 + .quad 0xbe1cf0976acada87 + .quad 0xc08623c5ec3733d0 + .quad 0xbe1cf066318a16ff + .quad 0xc08623c9a1274880 + .quad 0xbe1ceffaa7148798 + .quad 0xc08623cd54607820 + .quad 0xbe1cf23ab02e9b6e + .quad 0xc08623d105e45800 + .quad 0xbe1cefdfef7d4fde + .quad 0xc08623d4b5b47b20 + .quad 0xbe1cf17fece44f2b + .quad 0xc08623d863d27270 + .quad 0xbe1cf18f907d0d7c + .quad 0xc08623dc103fccb0 + .quad 0xbe1cee61fe072c98 + .quad 0xc08623dfbafe1668 + .quad 0xbe1cf022dd891e2f + .quad 0xc08623e3640eda20 + .quad 0xbe1ceecc1daf4358 + .quad 0xc08623e70b73a028 + .quad 0xbe1cf0173c4fa380 + .quad 0xc08623eab12deec8 + .quad 0xbe1cf16a2150c2f4 + .quad 0xc08623ee553f4a30 + .quad 0xbe1cf1bf980b1f4b + .quad 0xc08623f1f7a93480 + .quad 0xbe1cef8b731663c2 + .quad 0xc08623f5986d2dc0 + .quad 0xbe1cee9a664d7ef4 + .quad 0xc08623f9378cb3f0 + .quad 0xbe1cf1eda2af6400 + .quad 0xc08623fcd5094320 + .quad 0xbe1cf1923f9d68d7 + .quad 0xc086240070e45548 + .quad 0xbe1cf0747cd3e03a + .quad 0xc08624040b1f6260 + .quad 0xbe1cf22ee855bd6d + .quad 0xc0862407a3bbe078 + .quad 0xbe1cf0d57360c00b + .quad 0xc086240b3abb4398 + .quad 0xbe1ceebc815cd575 + .quad 0xc086240ed01efdd0 + .quad 0xbe1cf03bfb970951 + .quad 0xc086241263e87f50 + .quad 0xbe1cf16e74768529 + .quad 0xc0862415f6193658 + .quad 0xbe1cefec64b8becb + .quad 0xc086241986b28f30 + .quad 0xbe1cf0838d210baa + .quad 0xc086241d15b5f448 + .quad 0xbe1cf0ea86e75b11 + .quad 0xc0862420a324ce28 + .quad 0xbe1cf1708d11d805 + .quad 0xc08624242f008380 + .quad 0xbe1ceea988c5a417 + .quad 0xc0862427b94a7910 + .quad 0xbe1cef166a7bbca5 + .quad 0xc086242b420411d0 + .quad 0xbe1cf0c9d9e86a38 + .quad 0xc086242ec92eaee8 + .quad 0xbe1cef0946455411 + .quad 0xc08624324ecbaf98 + .quad 0xbe1cefea60907739 + .quad 0xc0862435d2dc7160 + .quad 0xbe1cf1ed0934ce42 + .quad 0xc086243955624ff8 + .quad 0xbe1cf191ba746c7d + .quad 0xc086243cd65ea548 + .quad 0xbe1ceeec78cf2a7e + .quad 0xc086244055d2c968 + .quad 0xbe1cef345284c119 + .quad 0xc0862443d3c012b8 + .quad 0xbe1cf24f77355219 + .quad 0xc08624475027d5e8 + .quad 0xbe1cf05bf087e114 + .quad 0xc086244acb0b65d0 + .quad 0xbe1cef3504a32189 + .quad 0xc086244e446c1398 + .quad 0xbe1ceff54b2a406f + .quad 0xc0862451bc4b2eb8 + .quad 0xbe1cf0757d54ed4f + .quad 0xc086245532aa04f0 + .quad 0xbe1cf0c8099fdfd5 + .quad 0xc0862458a789e250 + .quad 0xbe1cf0b173796a31 + .quad 0xc086245c1aec1138 + .quad 0xbe1cf11d8734540d + .quad 0xc086245f8cd1da60 + .quad 0xbe1cf1916a723ceb + .quad 0xc0862462fd3c84d8 + .quad 0xbe1cf19a911e1da7 + .quad 0xc08624666c2d5608 + .quad 0xbe1cf23a9ef72e4f + .quad 0xc0862469d9a591c0 + .quad 0xbe1cef503d947663 + .quad 0xc086246d45a67a18 + .quad 0xbe1cf0fceeb1a0b2 + .quad 0xc0862470b0314fa8 + .quad 0xbe1cf107e27e4fbc + .quad 0xc086247419475160 + .quad 0xbe1cf03dd9922331 + .quad 0xc086247780e9bc98 + .quad 0xbe1cefce1a10e129 + .quad 0xc086247ae719cd18 + .quad 0xbe1ceea47f73c4f6 + .quad 0xc086247e4bd8bd10 + .quad 0xbe1ceec0ac56d100 + .quad 0xc0862481af27c528 + .quad 0xbe1cee8a6593278a + .quad 0xc086248511081c70 + .quad 0xbe1cf2231dd9dec7 + .quad 0xc0862488717af888 + .quad 0xbe1cf0b4b8ed7da8 + .quad 0xc086248bd0818d68 + .quad 0xbe1cf1bd8d835002 + .quad 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0xbe1cf143efdd1fd0 + .quad 0xc0862882c24faff8 + .quad 0xbe1cee9896d016da + .quad 0xc0862884cf630e38 + .quad 0xbe1cf2186072f2cc + .quad 0xc0862886dbefeff0 + .quad 0xbe1cef9217633d34 + .quad 0xc0862888e7f699e0 + .quad 0xbe1cf05603549486 + .quad 0xc086288af37750b0 + .quad 0xbe1cef50fff513d3 + .quad 0xc086288cfe7258c0 + .quad 0xbe1cf127713b32d0 + .quad 0xc086288f08e7f650 + .quad 0xbe1cf05015520f3d + .quad 0xc086289112d86d58 + .quad 0xbe1cf12eb458b26f + .quad 0xc08628931c4401a8 + .quad 0xbe1cf22eae2887ed + .quad 0xc0862895252af6e0 + .quad 0xbe1cefdd6656dd2d + .quad 0xc08628972d8d9058 + .quad 0xbe1cf1048ea4e646 + .quad 0xc0862899356c1150 + .quad 0xbe1ceec4501167e9 + .quad 0xc086289b3cc6bcb8 + .quad 0xbe1cf0ad52becc3f + .quad 0xc086289d439dd568 + .quad 0xbe1cf0daa4e00e35 + .quad 0xc086289f49f19df8 + .quad 0xbe1cf00b80de8d6a + .quad 0xc08628a14fc258c8 + .quad 0xbe1cf1bcf2ea8464 + .quad 0xc08628a355104818 + .quad 0xbe1cf0435e2782b0 + .quad 0xc08628a559dbade0 + .quad 0xbe1cf0e3e1a5f56c + .quad 0xc08628a75e24cbf8 + .quad 0xbe1cefed9d5a721d + .quad 0xc08628a961ebe3f8 + .quad 0xbe1cf0d2d74321e2 + .quad 0xc08628ab65313750 + .quad 0xbe1cf24200eb55e9 + .quad 0xc08628ad67f50740 + .quad 0xbe1cf23e9d7cf979 + .quad 0xc08628af6a3794d0 + .quad 0xbe1cf23a088f421c + .quad 0xc08628b16bf920e0 + .quad 0xbe1cef2c1de1ab32 + .quad 0xc08628b36d39ec08 + .quad 0xbe1cf1abc231f7b2 + .quad 0xc08628b56dfa36d0 + .quad 0xbe1cf2074d5ba303 + .quad 0xc08628b76e3a4180 + .quad 0xbe1cf05cd5eed880 + .rept 48 + .byte 0 + .endr + +/* Lookup table with 9-bit index for + -log(mRcp), where mRcp is mantissa of 1/x 9-bit accurate reciprocal: + */ +.if .-__svml_dlog_data != _Log_LA_table +.err +.endif + .quad 0x8000000000000000 + .quad 0xbf5ff802a9ab10e6 + .quad 0xbf6ff00aa2b10bc0 + .quad 0xbf77ee11ebd82e94 + .quad 0xbf7fe02a6b106789 + .quad 0xbf83e7295d25a7d9 + .quad 0xbf87dc475f810a77 + .quad 0xbf8bcf712c74384c + .quad 0xbf8fc0a8b0fc03e4 + .quad 0xbf91d7f7eb9eebe7 + .quad 0xbf93cea44346a575 + .quad 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0xbfc3a8eb2d31a376 + .quad 0xbfc3dfc2b0ecc62a + .quad 0xbfc41682bf727bc0 + .quad 0xbfc44d2b6ccb7d1e + .quad 0xbfc483bccce6e3dd + .quad 0xbfc4ba36f39a55e5 + .quad 0xbfc4f099f4a230b2 + .quad 0xbfc526e5e3a1b438 + .quad 0xbfc55d1ad4232d6f + .quad 0xbfc59338d9982086 + .quad 0xbfc5c940075972b9 + .quad 0xbfc5ff3070a793d4 + .quad 0xbfc6350a28aaa758 + .quad 0xbfc66acd4272ad51 + .quad 0xbfc6a079d0f7aad2 + .quad 0xbfc6d60fe719d21d + .quad 0xbfc70b8f97a1aa75 + .quad 0xbfc740f8f54037a5 + .quad 0xbfc7764c128f2127 + .quad 0xbfc7ab890210d909 + .quad 0xbfc7e0afd630c274 + .quad 0xbfc815c0a14357eb + .quad 0xbfc84abb75865139 + .quad 0xbfc87fa06520c911 + .quad 0xbfc8b46f8223625b + .quad 0xbfc8e928de886d41 + .quad 0xbfc91dcc8c340bde + .quad 0xbfc9525a9cf456b4 + .quad 0xbfc986d3228180ca + .quad 0xbfc9bb362e7dfb83 + .quad 0xbfc9ef83d2769a34 + .quad 0xbfca23bc1fe2b563 + .quad 0xbfca57df28244dcd + .quad 0xbfca8becfc882f19 + .quad 0xbfcabfe5ae46124c + .quad 0xbfcaf3c94e80bff3 + .quad 0xbfcb2797ee46320c + .quad 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0x3f9432a925980cc1 + .quad 0x3f932db0ea132e22 + .quad 0x3f9228fb1fea2e28 + .quad 0x3f912487a5507f70 + .quad 0x3f90205658935847 + .quad 0x3f8e38ce3033310c + .quad 0x3f8c317384c75f06 + .quad 0x3f8a2a9c6c170462 + .quad 0x3f882448a388a2aa + .quad 0x3f861e77e8b53fc6 + .quad 0x3f841929f96832f0 + .quad 0x3f82145e939ef1e9 + .quad 0x3f8010157588de71 + .quad 0x3f7c189cbb0e27fb + .quad 0x3f78121214586b54 + .quad 0x3f740c8a747878e2 + .quad 0x3f70080559588b35 + .quad 0x3f680904828985c0 + .quad 0x3f60040155d5889e + .quad 0x3f50020055655889 + .quad 0x0000000000000000 + .rept 56 + .byte 0 + .endr + +/* Polynomial coefficients: */ +double_vector _poly_coeff_1 0x3fc9999cacdb4d0a +double_vector _poly_coeff_2 0xbfd0000148058ee1 +double_vector _poly_coeff_3 0x3fd55555555543c5 +double_vector _poly_coeff_4 0xbfdffffffffff81f + +/* Exponent mask */ +double_vector _ExpMask 0x000fffffffffffff + +/* 2^10 */ +double_vector _Two10 0x3f50000000000000 + +/* Minimum normal number */ +double_vector _MinNorm 0x0010000000000000 + +/* Maximum normal number */ +double_vector _MaxNorm 0x7fefffffffffffff + +/* Half of mantissa mask */ +double_vector _HalfMask 0xfffffffffc000000 + +/* 1.0 */ +double_vector _One 0x3ff0000000000000 + +/* log(2) high part */ +double_vector _L2H 0x3fe62e42fefa0000 + +/* log(2) low part */ +double_vector _L2L 0x3d7cf79abc9e0000 + +/* Work range threshold = 724 */ +double_vector _Threshold 0x4086a00000000000 + +/* Bias */ +double_vector _Bias 0x408ff80000000000 + +/* Bias (-1 bit) */ +double_vector _Bias1 0x408ff00000000000 + +/* log(2) */ +double_vector _L2 0x3fe62e42fefa39ef + +/* General purpose constants: + DP infinities, +/- */ +.if .-__svml_dlog_data != _dInfs +.err +.endif + .quad 0x7ff0000000000000 + .quad 0xfff0000000000000 + .rept 48 + .byte 0 + .endr + +/* DP 1.0, +/- */ +.if .-__svml_dlog_data != _dOnes +.err +.endif + .quad 0x3ff0000000000000 + .quad 0xbff0000000000000 + .rept 48 + .byte 0 + .endr + +/* DP 0.0, +/- */ +.if .-__svml_dlog_data != _dZeros +.err +.endif + .quad 0x0000000000000000 + .quad 0x8000000000000000 + .rept 48 + .byte 0 + .endr + .type __svml_dlog_data,@object + .size __svml_dlog_data,.-__svml_dlog_data diff --git a/sysdeps/x86_64/fpu/svml_d_log_data.h b/sysdeps/x86_64/fpu/svml_d_log_data.h new file mode 100644 index 0000000000..8ca55a8010 --- /dev/null +++ b/sysdeps/x86_64/fpu/svml_d_log_data.h @@ -0,0 +1,54 @@ +/* Offsets for data table for function log. + Copyright (C) 2014-2015 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef D_LOG_DATA_H +#define D_LOG_DATA_H + +#define _LogRcp_lookup -4218816 +#define _Log_HA_table 0 +#define _Log_LA_table 8256 +#define _poly_coeff_1 12416 +#define _poly_coeff_2 12480 +#define _poly_coeff_3 12544 +#define _poly_coeff_4 12608 +#define _ExpMask 12672 +#define _Two10 12736 +#define _MinNorm 12800 +#define _MaxNorm 12864 +#define _HalfMask 12928 +#define _One 12992 +#define _L2H 13056 +#define _L2L 13120 +#define _Threshold 13184 +#define _Bias 13248 +#define _Bias1 13312 +#define _L2 13376 +#define _dInfs 13440 +#define _dOnes 13504 +#define _dZeros 13568 + +.macro double_vector offset value +.if .-__svml_dlog_data != \offset +.err +.endif +.rept 8 +.quad \value +.endr +.endm + +#endif diff --git a/sysdeps/x86_64/fpu/test-double-vlen2-wrappers.c b/sysdeps/x86_64/fpu/test-double-vlen2-wrappers.c index 347aab5e8a..dfbc3d3708 100644 --- a/sysdeps/x86_64/fpu/test-double-vlen2-wrappers.c +++ b/sysdeps/x86_64/fpu/test-double-vlen2-wrappers.c @@ -24,3 +24,4 @@ VECTOR_WRAPPER (WRAPPER_NAME (cos), _ZGVbN2v_cos) VECTOR_WRAPPER (WRAPPER_NAME (sin), _ZGVbN2v_sin) +VECTOR_WRAPPER (WRAPPER_NAME (log), _ZGVbN2v_log) diff --git a/sysdeps/x86_64/fpu/test-double-vlen2.c b/sysdeps/x86_64/fpu/test-double-vlen2.c index 353b680039..a119bfc33a 100644 --- a/sysdeps/x86_64/fpu/test-double-vlen2.c +++ b/sysdeps/x86_64/fpu/test-double-vlen2.c @@ -20,5 +20,6 @@ #define TEST_VECTOR_cos 1 #define TEST_VECTOR_sin 1 +#define TEST_VECTOR_log 1 #include "libm-test.c" diff --git a/sysdeps/x86_64/fpu/test-double-vlen4-avx2-wrappers.c b/sysdeps/x86_64/fpu/test-double-vlen4-avx2-wrappers.c index 006c795d8b..6e01a8945f 100644 --- a/sysdeps/x86_64/fpu/test-double-vlen4-avx2-wrappers.c +++ b/sysdeps/x86_64/fpu/test-double-vlen4-avx2-wrappers.c @@ -27,3 +27,4 @@ VECTOR_WRAPPER (WRAPPER_NAME (cos), _ZGVdN4v_cos) VECTOR_WRAPPER (WRAPPER_NAME (sin), _ZGVdN4v_sin) +VECTOR_WRAPPER (WRAPPER_NAME (log), _ZGVdN4v_log) diff --git a/sysdeps/x86_64/fpu/test-double-vlen4-avx2.c b/sysdeps/x86_64/fpu/test-double-vlen4-avx2.c index 51247b7a48..ef6e1c2a42 100644 --- a/sysdeps/x86_64/fpu/test-double-vlen4-avx2.c +++ b/sysdeps/x86_64/fpu/test-double-vlen4-avx2.c @@ -23,6 +23,7 @@ #define TEST_VECTOR_cos 1 #define TEST_VECTOR_sin 1 +#define TEST_VECTOR_log 1 #define REQUIRE_AVX2 diff --git a/sysdeps/x86_64/fpu/test-double-vlen4-wrappers.c b/sysdeps/x86_64/fpu/test-double-vlen4-wrappers.c index b87454e864..e9f890573f 100644 --- a/sysdeps/x86_64/fpu/test-double-vlen4-wrappers.c +++ b/sysdeps/x86_64/fpu/test-double-vlen4-wrappers.c @@ -24,3 +24,4 @@ VECTOR_WRAPPER (WRAPPER_NAME (cos), _ZGVcN4v_cos) VECTOR_WRAPPER (WRAPPER_NAME (sin), _ZGVcN4v_sin) +VECTOR_WRAPPER (WRAPPER_NAME (log), _ZGVcN4v_log) diff --git a/sysdeps/x86_64/fpu/test-double-vlen4.c b/sysdeps/x86_64/fpu/test-double-vlen4.c index 4c1aefa979..71ea85cc0e 100644 --- a/sysdeps/x86_64/fpu/test-double-vlen4.c +++ b/sysdeps/x86_64/fpu/test-double-vlen4.c @@ -20,5 +20,6 @@ #define TEST_VECTOR_cos 1 #define TEST_VECTOR_sin 1 +#define TEST_VECTOR_log 1 #include "libm-test.c" diff --git a/sysdeps/x86_64/fpu/test-double-vlen8-wrappers.c b/sysdeps/x86_64/fpu/test-double-vlen8-wrappers.c index b789f5e18d..290d59c74c 100644 --- a/sysdeps/x86_64/fpu/test-double-vlen8-wrappers.c +++ b/sysdeps/x86_64/fpu/test-double-vlen8-wrappers.c @@ -24,3 +24,4 @@ VECTOR_WRAPPER (WRAPPER_NAME (cos), _ZGVeN8v_cos) VECTOR_WRAPPER (WRAPPER_NAME (sin), _ZGVeN8v_sin) +VECTOR_WRAPPER (WRAPPER_NAME (log), _ZGVeN8v_log) diff --git a/sysdeps/x86_64/fpu/test-double-vlen8.c b/sysdeps/x86_64/fpu/test-double-vlen8.c index 99982800ee..e2f2cfef2e 100644 --- a/sysdeps/x86_64/fpu/test-double-vlen8.c +++ b/sysdeps/x86_64/fpu/test-double-vlen8.c @@ -20,6 +20,7 @@ #define TEST_VECTOR_cos 1 #define TEST_VECTOR_sin 1 +#define TEST_VECTOR_log 1 #define REQUIRE_AVX512F |