diff options
| -rw-r--r-- | ChangeLog | 12 | ||||
| -rw-r--r-- | sysdeps/powerpc/fpu/fedisblxcpt.c | 2 | ||||
| -rw-r--r-- | sysdeps/powerpc/fpu/feenablxcpt.c | 2 | ||||
| -rw-r--r-- | sysdeps/powerpc/fpu/fegetexcept.c | 2 | ||||
| -rw-r--r-- | sysdeps/powerpc/fpu/fegetmode.c | 2 | ||||
| -rw-r--r-- | sysdeps/powerpc/fpu/fenv_libc.h | 6 | ||||
| -rw-r--r-- | sysdeps/powerpc/fpu/fesetenv.c | 2 | ||||
| -rw-r--r-- | sysdeps/powerpc/fpu/fesetmode.c | 2 |
8 files changed, 21 insertions, 9 deletions
diff --git a/ChangeLog b/ChangeLog index a1192a3a70..6c28351c37 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,5 +1,17 @@ 2019-09-27 Paul A. Clarke <pc@us.ibm.com> + * sysdeps/powerpc/fpu/fenv_libc.h (fegetenv_status): Rename to + fegetenv_control. + * sysdeps/powerpc/fpu/fedisblxcpt.c (fedisableexcept): Accommodate + rename of fegetenv_status to fegetenv_control. + * sysdeps/powerpc/fpu/feenablxcpt.c (feenableexcept): Likewise. + * sysdeps/powerpc/fpu/fegetexcept.c (__fegetexcept): Likewise. + * sysdeps/powerpc/fpu/fegetmode.c (fegetmode): Likewise. + * sysdeps/powerpc/fpu/fesetenv.c (__fesetenv): Likewise. + * sysdeps/powerpc/fpu/fesetmode.c (fesetmode): Likewise. + +2019-09-27 Paul A. Clarke <pc@us.ibm.com> + * sysdeps/powerpc/fpu/fenv_libc.h (__fesetround_inline): Use 'mffscrn' instruction on POWER9. (__fesetround_inline_nocheck): Likewise. diff --git a/sysdeps/powerpc/fpu/fedisblxcpt.c b/sysdeps/powerpc/fpu/fedisblxcpt.c index 0d9bf00574..870cfc8dbc 100644 --- a/sysdeps/powerpc/fpu/fedisblxcpt.c +++ b/sysdeps/powerpc/fpu/fedisblxcpt.c @@ -26,7 +26,7 @@ fedisableexcept (int excepts) int result, new; /* Get current exception mask to return. */ - fe.fenv = curr.fenv = fegetenv_status (); + fe.fenv = curr.fenv = fegetenv_control (); result = fenv_reg_to_exceptions (fe.l); if ((excepts & FE_ALL_INVALID) == FE_ALL_INVALID) diff --git a/sysdeps/powerpc/fpu/feenablxcpt.c b/sysdeps/powerpc/fpu/feenablxcpt.c index cf670b86d1..43f6482f43 100644 --- a/sysdeps/powerpc/fpu/feenablxcpt.c +++ b/sysdeps/powerpc/fpu/feenablxcpt.c @@ -26,7 +26,7 @@ feenableexcept (int excepts) int result, new; /* Get current exception mask to return. */ - fe.fenv = curr.fenv = fegetenv_status (); + fe.fenv = curr.fenv = fegetenv_control (); result = fenv_reg_to_exceptions (fe.l); if ((excepts & FE_ALL_INVALID) == FE_ALL_INVALID) diff --git a/sysdeps/powerpc/fpu/fegetexcept.c b/sysdeps/powerpc/fpu/fegetexcept.c index bd27a807ed..179e3c4e81 100644 --- a/sysdeps/powerpc/fpu/fegetexcept.c +++ b/sysdeps/powerpc/fpu/fegetexcept.c @@ -24,7 +24,7 @@ __fegetexcept (void) { fenv_union_t fe; - fe.fenv = fegetenv_status (); + fe.fenv = fegetenv_control (); return fenv_reg_to_exceptions (fe.l); } diff --git a/sysdeps/powerpc/fpu/fegetmode.c b/sysdeps/powerpc/fpu/fegetmode.c index 0e0a01c708..65c5ebe56b 100644 --- a/sysdeps/powerpc/fpu/fegetmode.c +++ b/sysdeps/powerpc/fpu/fegetmode.c @@ -21,6 +21,6 @@ int fegetmode (femode_t *modep) { - *modep = fegetenv_status (); + *modep = fegetenv_control (); return 0; } diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h index 06bd9bad4c..17667d0a34 100644 --- a/sysdeps/powerpc/fpu/fenv_libc.h +++ b/sysdeps/powerpc/fpu/fenv_libc.h @@ -60,7 +60,7 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden; 'mffs' on architectures older than "power9" because the additional bits set for 'mffsl' are "don't care" for 'mffs'. 'mffs' is a superset of 'mffsl'. */ -#define fegetenv_status() \ +#define fegetenv_control() \ ({register double __fr; \ __asm__ __volatile__ ( \ ".machine push; .machine \"power9\"; mffsl %0; .machine pop" \ @@ -84,7 +84,7 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden; __fr.fenv; \ }) -/* Like fegetenv_status, but also sets the rounding mode. */ +/* Like fegetenv_control, but also sets the rounding mode. */ #ifdef _ARCH_PWR9 #define fegetenv_and_set_rn(rn) __fe_mffscrn (rn) #else @@ -115,7 +115,7 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden; /* Set the last 2 nibbles of the FPSCR, which contain the exception enables and the rounding mode. - 'fegetenv_status' retrieves these bits by reading the FPSCR. */ + 'fegetenv_control' retrieves these bits by reading the FPSCR. */ #define fesetenv_mode(env) __builtin_mtfsf (0b00000011, (env)); /* This very handy macro: diff --git a/sysdeps/powerpc/fpu/fesetenv.c b/sysdeps/powerpc/fpu/fesetenv.c index 949d916d76..fc7b8192e2 100644 --- a/sysdeps/powerpc/fpu/fesetenv.c +++ b/sysdeps/powerpc/fpu/fesetenv.c @@ -26,7 +26,7 @@ __fesetenv (const fenv_t *envp) /* get the currently set exceptions. */ new.fenv = *envp; - old.fenv = fegetenv_status (); + old.fenv = fegetenv_control (); __TEST_AND_EXIT_NON_STOP (old.l, new.l); __TEST_AND_ENTER_NON_STOP (old.l, new.l); diff --git a/sysdeps/powerpc/fpu/fesetmode.c b/sysdeps/powerpc/fpu/fesetmode.c index 90d86a969f..1e9a874efa 100644 --- a/sysdeps/powerpc/fpu/fesetmode.c +++ b/sysdeps/powerpc/fpu/fesetmode.c @@ -27,7 +27,7 @@ fesetmode (const femode_t *modep) /* Logic regarding enabled exceptions as in fesetenv. */ new.fenv = *modep; - old.fenv = fegetenv_status (); + old.fenv = fegetenv_control (); new.l = (new.l & ~FPSCR_STATUS_MASK) | (old.l & FPSCR_STATUS_MASK); if (old.l == new.l) |