diff options
| -rw-r--r-- | sysdeps/x86/cpu-features.c | 2 | ||||
| -rw-r--r-- | sysdeps/x86/dl-cacheinfo.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c index 525828f59c..9ac195810f 100644 --- a/sysdeps/x86/cpu-features.c +++ b/sysdeps/x86/cpu-features.c @@ -579,7 +579,7 @@ intel_get_fam6_microarch (unsigned int model, else -> Skylake-avx512 - These are all microarchitecturally indentical, so use + These are all microarchitecturally identical, so use Skylake-avx512 for all of them. */ return INTEL_BIGCORE_SKYLAKE_AVX512; diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h index fb1a6cf4a9..c98fa57a7b 100644 --- a/sysdeps/x86/dl-cacheinfo.h +++ b/sysdeps/x86/dl-cacheinfo.h @@ -745,7 +745,7 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) /* The default setting for the non_temporal threshold is [1/8, 1/2] of size of the chip's cache (depending on `cachesize_non_temporal_divisor` which - is microarch specific. The defeault is 1/4). For most Intel and AMD + is microarch specific. The default is 1/4). For most Intel and AMD processors with an initial release date between 2017 and 2023, a thread's typical share of the cache is from 18-64MB. Using a reasonable size fraction of L3 is meant to estimate the point where non-temporal stores |