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| -rw-r--r-- | ChangeLog | 2 | ||||
| -rw-r--r-- | manual/platform.texi | 19 |
2 files changed, 21 insertions, 0 deletions
diff --git a/ChangeLog b/ChangeLog index ec9b4757d1..ec0cce9c76 100644 --- a/ChangeLog +++ b/ChangeLog @@ -4,6 +4,8 @@ PREINIT_FUNCTION when defined. * manual/math.texi: RISC-V supports _Float128 and _Float64x. * config.h.in: Regenerate. + * manual/platform.texi: Add RISC-V documenation for + __riscv_flush_icache. 2018-01-29 Florian Weimer <fweimer@redhat.com> diff --git a/manual/platform.texi b/manual/platform.texi index cb166641fb..b8721a0712 100644 --- a/manual/platform.texi +++ b/manual/platform.texi @@ -6,6 +6,7 @@ @menu * PowerPC:: Facilities Specific to the PowerPC Architecture +* RISC-V:: Facilities Specific to the RISC-V Architecture @end menu @node PowerPC @@ -115,3 +116,21 @@ problem-state programs. If the program priority is medium high when the time interval expires or if an attempt is made to set the priority to medium high when it is not allowed, the priority is set to medium. @end deftypefun + +@node RISC-V +@appendixsec RISC-V-specific Facilities + +Cache management facilities specific to RISC-V systems that implement the Linux +ABI are declared in @file{sys/cachectl.h}. + +@deftypefun {void} __riscv_flush_icache(void *@var{start}, void *@var{end}, unsigned long int @var{flags}) +@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}} +Enforce ordering between stores and instruction cache fetches. The range of +addresses over which ordering is enforced is specified by @var{start} and +@var{end}. The @var{flags} argument controls the extent of this ordering, with +the default behavior (a @var{flags} value of 0) being to enforce the fence on +all threads in the current process. Setting the +@code{SYS_RISCV_FLUSH_ICACHE_LOCAL} bit allows users to indicate that enforcing +ordering on only the current thread is necessary. All other flag bits are +reserved. +@end deftypefun |