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| author | Andrew Senkevich <andrew.senkevich@intel.com> | 2015-06-08 14:07:59 +0300 |
|---|---|---|
| committer | Andrew Senkevich <andrew.senkevich@intel.com> | 2015-06-08 14:07:59 +0300 |
| commit | 5fe2a126d115e6b3220886f416b6b544252f8589 (patch) | |
| tree | 2d0b7b7fb57135bc5885bcc0a771c9e99a52c734 /wcsmbs/mbsrtowcs.c | |
| parent | 3ac3ff325d4042c8a8e20821195938601994d8f8 (diff) | |
| download | glibc-5fe2a126d115e6b3220886f416b6b544252f8589.tar.gz glibc-5fe2a126d115e6b3220886f416b6b544252f8589.tar.xz glibc-5fe2a126d115e6b3220886f416b6b544252f8589.zip | |
This patch adds detection of availability for AVX512F and AVX512DQ ISAs.
* sysdeps/x86_64/multiarch/init-arch.h (bit_AVX512F_Usable,
bit_AVX512DQ_Usable, bit_Opmask_state, bit_ZMM0_15_state,
bit_ZMM16_31_state): New macro.
* sysdeps/x86_64/multiarch/init-arch.c (__init_cpu_features):
Check and set bit_AVX512F_Usable, bit_AVX512DQ_Usable.
Diffstat (limited to 'wcsmbs/mbsrtowcs.c')
0 files changed, 0 insertions, 0 deletions