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author | Richard Henderson <rth@twiddle.net> | 2017-11-03 16:38:16 +0000 |
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committer | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2017-11-03 16:40:27 +0000 |
commit | 6d58ce5e5072945d44f2dba83ad16cd6febd056c (patch) | |
tree | 35cd666ef3c3feb4130d963d08620734ef4bc51c /wcsmbs/Makefile | |
parent | 659ca267360e1c1f64eea9205bb81cb5e9049908 (diff) | |
download | glibc-6d58ce5e5072945d44f2dba83ad16cd6febd056c.tar.gz glibc-6d58ce5e5072945d44f2dba83ad16cd6febd056c.tar.xz glibc-6d58ce5e5072945d44f2dba83ad16cd6febd056c.zip |
aarch64: Guess L1 cache linesize for aarch64
Using the cache hierarchy linesize minimum in CTR_EL0. See the comment within the code for rationale. * sysdeps/unix/sysv/linux/aarch64/sysconf.c: New file.
Diffstat (limited to 'wcsmbs/Makefile')
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