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| author | Andreas Schwab <schwab@suse.de> | 2014-10-21 11:09:19 +0200 |
|---|---|---|
| committer | Andreas Schwab <schwab@suse.de> | 2014-10-27 10:44:28 +0100 |
| commit | 3574f2fdf3827d4953d19a89063e517263b5df85 (patch) | |
| tree | cdbe317761f280507d91b213133bf1cde3eb2951 /sysdeps | |
| parent | 461a7b1e4551ee9018f7542c21ff32b0f9872e7f (diff) | |
| download | glibc-3574f2fdf3827d4953d19a89063e517263b5df85.tar.gz glibc-3574f2fdf3827d4953d19a89063e517263b5df85.tar.xz glibc-3574f2fdf3827d4953d19a89063e517263b5df85.zip | |
Fix misdetected Slow_SSE4_2 cpu feature bit (bug 17501)
Diffstat (limited to 'sysdeps')
| -rw-r--r-- | sysdeps/i386/i686/multiarch/strcasecmp.S | 4 | ||||
| -rw-r--r-- | sysdeps/i386/i686/multiarch/strcmp.S | 4 | ||||
| -rw-r--r-- | sysdeps/i386/i686/multiarch/strncase.S | 4 | ||||
| -rw-r--r-- | sysdeps/x86_64/multiarch/strcmp.S | 8 |
4 files changed, 10 insertions, 10 deletions
diff --git a/sysdeps/i386/i686/multiarch/strcasecmp.S b/sysdeps/i386/i686/multiarch/strcasecmp.S index 4f2de4f37b..57ccef51a0 100644 --- a/sysdeps/i386/i686/multiarch/strcasecmp.S +++ b/sysdeps/i386/i686/multiarch/strcasecmp.S @@ -37,7 +37,7 @@ ENTRY(__strcasecmp) leal __strcasecmp_ssse3@GOTOFF(%ebx), %eax testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx) jz 2f - testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx) + testl $bit_Slow_SSE4_2, FEATURE_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx) jnz 2f leal __strcasecmp_sse4_2@GOTOFF(%ebx), %eax 2: popl %ebx @@ -58,7 +58,7 @@ ENTRY(__strcasecmp) leal __strcasecmp_ssse3, %eax testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features jz 2f - testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features + testl $bit_Slow_SSE4_2, FEATURE_OFFSET+index_Slow_SSE4_2+__cpu_features jnz 2f leal __strcasecmp_sse4_2, %eax 2: ret diff --git a/sysdeps/i386/i686/multiarch/strcmp.S b/sysdeps/i386/i686/multiarch/strcmp.S index 2ad6bf4212..23cbd6f3c5 100644 --- a/sysdeps/i386/i686/multiarch/strcmp.S +++ b/sysdeps/i386/i686/multiarch/strcmp.S @@ -68,7 +68,7 @@ ENTRY(STRCMP) leal __STRCMP_SSSE3@GOTOFF(%ebx), %eax testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx) jz 2f - testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx) + testl $bit_Slow_SSE4_2, FEATURE_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx) jnz 2f leal __STRCMP_SSE4_2@GOTOFF(%ebx), %eax 2: popl %ebx @@ -89,7 +89,7 @@ ENTRY(STRCMP) leal __STRCMP_SSSE3, %eax testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features jz 2f - testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features + testl $bit_Slow_SSE4_2, FEATURE_OFFSET+index_Slow_SSE4_2+__cpu_features jnz 2f leal __STRCMP_SSE4_2, %eax 2: ret diff --git a/sysdeps/i386/i686/multiarch/strncase.S b/sysdeps/i386/i686/multiarch/strncase.S index 9b4cfa063a..41644a5876 100644 --- a/sysdeps/i386/i686/multiarch/strncase.S +++ b/sysdeps/i386/i686/multiarch/strncase.S @@ -37,7 +37,7 @@ ENTRY(__strncasecmp) leal __strncasecmp_ssse3@GOTOFF(%ebx), %eax testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx) jz 2f - testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx) + testl $bit_Slow_SSE4_2, FEATURE_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx) jnz 2f leal __strncasecmp_sse4_2@GOTOFF(%ebx), %eax 2: popl %ebx @@ -58,7 +58,7 @@ ENTRY(__strncasecmp) leal __strncasecmp_ssse3, %eax testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features jz 2f - testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features + testl $bit_Slow_SSE4_2, FEATURE_OFFSET+index_Slow_SSE4_2+__cpu_features jnz 2f leal __strncasecmp_sse4_2, %eax 2: ret diff --git a/sysdeps/x86_64/multiarch/strcmp.S b/sysdeps/x86_64/multiarch/strcmp.S index f3e0ca1259..bd71714e0b 100644 --- a/sysdeps/x86_64/multiarch/strcmp.S +++ b/sysdeps/x86_64/multiarch/strcmp.S @@ -91,10 +91,10 @@ ENTRY(STRCMP) 1: #ifdef USE_AS_STRCMP leaq __strcmp_sse2_unaligned(%rip), %rax - testl $bit_Fast_Unaligned_Load, __cpu_features+CPUID_OFFSET+index_Fast_Unaligned_Load(%rip) + testl $bit_Fast_Unaligned_Load, __cpu_features+FEATURE_OFFSET+index_Fast_Unaligned_Load(%rip) jnz 3f #else - testl $bit_Slow_SSE4_2, __cpu_features+CPUID_OFFSET+index_Slow_SSE4_2(%rip) + testl $bit_Slow_SSE4_2, __cpu_features+FEATURE_OFFSET+index_Slow_SSE4_2(%rip) jnz 2f leaq STRCMP_SSE42(%rip), %rax testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip) @@ -120,7 +120,7 @@ ENTRY(__strcasecmp) testl $bit_AVX_Usable, __cpu_features+FEATURE_OFFSET+index_AVX_Usable(%rip) jnz 3f # endif - testl $bit_Slow_SSE4_2, __cpu_features+CPUID_OFFSET+index_Slow_SSE4_2(%rip) + testl $bit_Slow_SSE4_2, __cpu_features+FEATURE_OFFSET+index_Slow_SSE4_2(%rip) jnz 2f leaq __strcasecmp_sse42(%rip), %rax testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip) @@ -146,7 +146,7 @@ ENTRY(__strncasecmp) testl $bit_AVX_Usable, __cpu_features+FEATURE_OFFSET+index_AVX_Usable(%rip) jnz 3f # endif - testl $bit_Slow_SSE4_2, __cpu_features+CPUID_OFFSET+index_Slow_SSE4_2(%rip) + testl $bit_Slow_SSE4_2, __cpu_features+FEATURE_OFFSET+index_Slow_SSE4_2(%rip) jnz 2f leaq __strncasecmp_sse42(%rip), %rax testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip) |