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| author | Maciej W. Rozycki <macro@codesourcery.com> | 2014-05-16 22:46:53 +0100 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@codesourcery.com> | 2014-05-16 23:10:29 +0100 |
| commit | deb0f7f6a825f2a90220bc4e1053d70876efb150 (patch) | |
| tree | a2f6d99748c0f9e56a9cb3d61b3faf22e8873743 /sysdeps | |
| parent | 79520f4bd611602f5bdb2b50979cf75bb5ac2968 (diff) | |
| download | glibc-deb0f7f6a825f2a90220bc4e1053d70876efb150.tar.gz glibc-deb0f7f6a825f2a90220bc4e1053d70876efb150.tar.xz glibc-deb0f7f6a825f2a90220bc4e1053d70876efb150.zip | |
ARM: soft-fp NaN representation correction
Commit 7d92b78723848ae616709eb8f0191ea067025b18 [Fix ARM NAN fraction bits.] removed all the bits set from NANFRAC macros and, when propagated to libgcc, regressed gcc.dg/torture/builtin-math-7.c on soft-fp arm-eabi targets, currently ARMv6-M (`-march=armv6-m -mthumb') only. This is because when used to construct a NaN in the semi-raw mode, they now build an infinity instead. Consequently operations such as (Inf - Inf) now produce Inf rather than NaN. The change worked for the original test case, posted with PR libgcc/60166, because division is made in the canonical mode, where the quiet bit is set separately, from the fp class. This change brings the quiet bit back to these macros, making semi-raw mode calculations produce the expected results again.
Diffstat (limited to 'sysdeps')
| -rw-r--r-- | sysdeps/arm/soft-fp/sfp-machine.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/sysdeps/arm/soft-fp/sfp-machine.h b/sysdeps/arm/soft-fp/sfp-machine.h index 32697fef44..2e7c156294 100644 --- a/sysdeps/arm/soft-fp/sfp-machine.h +++ b/sysdeps/arm/soft-fp/sfp-machine.h @@ -21,9 +21,9 @@ #define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y) #define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y) -#define _FP_NANFRAC_S 0 -#define _FP_NANFRAC_D 0, 0 -#define _FP_NANFRAC_Q 0, 0, 0, 0 +#define _FP_NANFRAC_S _FP_QNANBIT_S +#define _FP_NANFRAC_D _FP_QNANBIT_D, 0 +#define _FP_NANFRAC_Q _FP_QNANBIT_Q, 0, 0, 0 #define _FP_NANSIGN_S 0 #define _FP_NANSIGN_D 0 #define _FP_NANSIGN_Q 0 |