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author | Ian Bolton <ian.bolton@arm.com> | 2014-04-24 07:15:33 +0100 |
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committer | Marcus Shawcroft <marcus.shawcroft@linaro.org> | 2014-04-24 07:15:33 +0100 |
commit | e5e0d9a4f632735cf3bb440eecb5caee5eea44c1 (patch) | |
tree | 51c5774783bb0479b35a33f9a22b86db00c20cbe /sysdeps | |
parent | bacc75f7be11656387c239831f490155f5fb3700 (diff) | |
download | glibc-e5e0d9a4f632735cf3bb440eecb5caee5eea44c1.tar.gz glibc-e5e0d9a4f632735cf3bb440eecb5caee5eea44c1.tar.xz glibc-e5e0d9a4f632735cf3bb440eecb5caee5eea44c1.zip |
[AArch64] Suppress unnecessary FPSR and FPCR writes.
Diffstat (limited to 'sysdeps')
-rw-r--r-- | sysdeps/aarch64/fpu/fclrexcpt.c | 6 | ||||
-rw-r--r-- | sysdeps/aarch64/fpu/fedisblxcpt.c | 6 | ||||
-rw-r--r-- | sysdeps/aarch64/fpu/feenablxcpt.c | 6 | ||||
-rw-r--r-- | sysdeps/aarch64/fpu/feholdexcpt.c | 14 | ||||
-rw-r--r-- | sysdeps/aarch64/fpu/fesetenv.c | 28 | ||||
-rw-r--r-- | sysdeps/aarch64/fpu/fesetround.c | 6 | ||||
-rw-r--r-- | sysdeps/aarch64/fpu/fsetexcptflg.c | 8 |
7 files changed, 46 insertions, 28 deletions
diff --git a/sysdeps/aarch64/fpu/fclrexcpt.c b/sysdeps/aarch64/fpu/fclrexcpt.c index 531269f9cf..b24f0ffbbc 100644 --- a/sysdeps/aarch64/fpu/fclrexcpt.c +++ b/sysdeps/aarch64/fpu/fclrexcpt.c @@ -23,13 +23,15 @@ int feclearexcept (int excepts) { fpu_fpsr_t fpsr; + fpu_fpsr_t fpsr_new; excepts &= FE_ALL_EXCEPT; _FPU_GETFPSR (fpsr); - fpsr = (fpsr & ~FE_ALL_EXCEPT) | (fpsr & FE_ALL_EXCEPT & ~excepts); + fpsr_new = (fpsr & ~FE_ALL_EXCEPT) | (fpsr & FE_ALL_EXCEPT & ~excepts); - _FPU_SETFPSR (fpsr); + if (fpsr != fpsr_new) + _FPU_SETFPSR (fpsr_new); return 0; } diff --git a/sysdeps/aarch64/fpu/fedisblxcpt.c b/sysdeps/aarch64/fpu/fedisblxcpt.c index 719d52f60a..c43335c4e5 100644 --- a/sysdeps/aarch64/fpu/fedisblxcpt.c +++ b/sysdeps/aarch64/fpu/fedisblxcpt.c @@ -23,6 +23,7 @@ int fedisableexcept (int excepts) { fpu_control_t fpcr; + fpu_control_t fpcr_new; int original_excepts; _FPU_GETCW (fpcr); @@ -31,9 +32,10 @@ fedisableexcept (int excepts) excepts &= FE_ALL_EXCEPT; - fpcr &= ~(excepts << FE_EXCEPT_SHIFT); + fpcr_new = fpcr & ~(excepts << FE_EXCEPT_SHIFT); - _FPU_SETCW (fpcr); + if (fpcr != fpcr_new) + _FPU_SETCW (fpcr_new); return original_excepts; } diff --git a/sysdeps/aarch64/fpu/feenablxcpt.c b/sysdeps/aarch64/fpu/feenablxcpt.c index 07a4bbb58e..70e413c9f6 100644 --- a/sysdeps/aarch64/fpu/feenablxcpt.c +++ b/sysdeps/aarch64/fpu/feenablxcpt.c @@ -23,6 +23,7 @@ int feenableexcept (int excepts) { fpu_control_t fpcr; + fpu_control_t fpcr_new; int original_excepts; _FPU_GETCW (fpcr); @@ -31,9 +32,10 @@ feenableexcept (int excepts) excepts &= FE_ALL_EXCEPT; - fpcr |= (excepts << FE_EXCEPT_SHIFT); + fpcr_new = fpcr | (excepts << FE_EXCEPT_SHIFT); - _FPU_SETCW (fpcr); + if (fpcr != fpcr_new) + _FPU_SETCW (fpcr_new); /* Trapping exceptions are optional in AArch64 the relevant enable bits in FPCR are RES0 hence the absence of support can be diff --git a/sysdeps/aarch64/fpu/feholdexcpt.c b/sysdeps/aarch64/fpu/feholdexcpt.c index 0514ac15b5..973ba4a56a 100644 --- a/sysdeps/aarch64/fpu/feholdexcpt.c +++ b/sysdeps/aarch64/fpu/feholdexcpt.c @@ -22,8 +22,10 @@ int feholdexcept (fenv_t *envp) { - fpu_fpsr_t fpsr; fpu_control_t fpcr; + fpu_control_t fpcr_new; + fpu_fpsr_t fpsr; + fpu_fpsr_t fpsr_new; _FPU_GETCW (fpcr); envp->__fpcr = fpcr; @@ -32,14 +34,16 @@ feholdexcept (fenv_t *envp) envp->__fpsr = fpsr; /* Now set all exceptions to non-stop. */ - fpcr &= ~(FE_ALL_EXCEPT << FE_EXCEPT_SHIFT); + fpcr_new = fpcr & ~(FE_ALL_EXCEPT << FE_EXCEPT_SHIFT); /* And clear all exception flags. */ - fpsr &= ~FE_ALL_EXCEPT; + fpsr_new = fpsr & ~FE_ALL_EXCEPT; - _FPU_SETFPSR (fpsr); + if (fpsr != fpsr_new) + _FPU_SETFPSR (fpsr_new); - _FPU_SETCW (fpcr); + if (fpcr != fpcr_new) + _FPU_SETCW (fpcr_new); return 0; } diff --git a/sysdeps/aarch64/fpu/fesetenv.c b/sysdeps/aarch64/fpu/fesetenv.c index a2434e37b0..30193e955f 100644 --- a/sysdeps/aarch64/fpu/fesetenv.c +++ b/sysdeps/aarch64/fpu/fesetenv.c @@ -23,34 +23,38 @@ int fesetenv (const fenv_t *envp) { fpu_control_t fpcr; - fpu_fpsr_t fpsr; + fpu_control_t fpcr_new; fpu_control_t updated_fpcr; + fpu_fpsr_t fpsr; + fpu_fpsr_t fpsr_new; _FPU_GETCW (fpcr); _FPU_GETFPSR (fpsr); - fpcr &= _FPU_RESERVED; - fpsr &= _FPU_FPSR_RESERVED; + fpcr_new = fpcr & _FPU_RESERVED; + fpsr_new = fpsr & _FPU_FPSR_RESERVED; if (envp == FE_DFL_ENV) { - fpcr |= _FPU_DEFAULT; - fpsr |= _FPU_FPSR_DEFAULT; + fpcr_new |= _FPU_DEFAULT; + fpsr_new |= _FPU_FPSR_DEFAULT; } else if (envp == FE_NOMASK_ENV) { - fpcr |= _FPU_FPCR_IEEE; - fpsr |= _FPU_FPSR_IEEE; + fpcr_new |= _FPU_FPCR_IEEE; + fpsr_new |= _FPU_FPSR_IEEE; } else { - fpcr |= envp->__fpcr & ~_FPU_RESERVED; - fpsr |= envp->__fpsr & ~_FPU_FPSR_RESERVED; + fpcr_new |= envp->__fpcr & ~_FPU_RESERVED; + fpsr_new |= envp->__fpsr & ~_FPU_FPSR_RESERVED; } - _FPU_SETFPSR (fpsr); + if (fpsr != fpsr_new) + _FPU_SETFPSR (fpsr_new); - _FPU_SETCW (fpcr); + if (fpcr != fpcr_new) + _FPU_SETCW (fpcr_new); /* Trapping exceptions are optional in AArch64 the relevant enable bits in FPCR are RES0 hence the absence of support can be @@ -58,7 +62,7 @@ fesetenv (const fenv_t *envp) value. */ _FPU_GETCW (updated_fpcr); - if ((updated_fpcr & fpcr) != fpcr) + if ((updated_fpcr & fpcr_new) != fpcr_new) return 1; return 0; diff --git a/sysdeps/aarch64/fpu/fesetround.c b/sysdeps/aarch64/fpu/fesetround.c index 40a05f6582..225096ae7c 100644 --- a/sysdeps/aarch64/fpu/fesetround.c +++ b/sysdeps/aarch64/fpu/fesetround.c @@ -23,6 +23,7 @@ int fesetround (int round) { fpu_control_t fpcr; + fpu_control_t fpcr_new; switch (round) { @@ -31,9 +32,10 @@ fesetround (int round) case FE_DOWNWARD: case FE_TOWARDZERO: _FPU_GETCW (fpcr); - fpcr = (fpcr & ~FE_TOWARDZERO) | round; + fpcr_new = (fpcr & ~FE_TOWARDZERO) | round; - _FPU_SETCW (fpcr); + if (fpcr != fpcr_new) + _FPU_SETCW (fpcr_new); return 0; default: diff --git a/sysdeps/aarch64/fpu/fsetexcptflg.c b/sysdeps/aarch64/fpu/fsetexcptflg.c index 49cd1e467f..60bb1c9e96 100644 --- a/sysdeps/aarch64/fpu/fsetexcptflg.c +++ b/sysdeps/aarch64/fpu/fsetexcptflg.c @@ -24,16 +24,18 @@ int fesetexceptflag (const fexcept_t *flagp, int excepts) { fpu_fpsr_t fpsr; + fpu_fpsr_t fpsr_new; /* Get the current environment. */ _FPU_GETFPSR (fpsr); /* Set the desired exception mask. */ - fpsr &= ~(excepts & FE_ALL_EXCEPT); - fpsr |= (*flagp & excepts & FE_ALL_EXCEPT); + fpsr_new = fpsr & ~(excepts & FE_ALL_EXCEPT); + fpsr_new |= (*flagp & excepts & FE_ALL_EXCEPT); /* Save state back to the FPU. */ - _FPU_SETFPSR (fpsr); + if (fpsr != fpsr_new) + _FPU_SETFPSR (fpsr_new); return 0; } |