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| author | David S. Miller <davem@davemloft.net> | 2012-04-25 22:24:00 -0700 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2012-04-25 22:24:00 -0700 |
| commit | cfa1f3e8651f43ea8031b4fb6e491253261f95d1 (patch) | |
| tree | 2e8713aaba484a5347892edb25a8dd9b874330f7 /sysdeps | |
| parent | 6e236b92765cdafb46d19e4907471699accc8269 (diff) | |
| download | glibc-cfa1f3e8651f43ea8031b4fb6e491253261f95d1.tar.gz glibc-cfa1f3e8651f43ea8031b4fb6e491253261f95d1.tar.xz glibc-cfa1f3e8651f43ea8031b4fb6e491253261f95d1.zip | |
Restore non-v9 32-bit sparc build.
* sysdeps/sparc/sparc32/bits/atomic.h: Include sysdep.h to get HWCAP_* values only after the memory barriers have been defined. (atomic_full_barrier): Define. (atomic_read_barrier): Define. (atomic_write_barrier): Define.
Diffstat (limited to 'sysdeps')
| -rw-r--r-- | sysdeps/sparc/sparc32/bits/atomic.h | 34 |
1 files changed, 33 insertions, 1 deletions
diff --git a/sysdeps/sparc/sparc32/bits/atomic.h b/sysdeps/sparc/sparc32/bits/atomic.h index 4f783fbc30..fb16fc29d5 100644 --- a/sysdeps/sparc/sparc32/bits/atomic.h +++ b/sysdeps/sparc/sparc32/bits/atomic.h @@ -21,7 +21,6 @@ #define _BITS_ATOMIC_H 1 #include <stdint.h> -#include <sysdep.h> typedef int8_t atomic8_t; typedef uint8_t uatomic8_t; @@ -231,6 +230,10 @@ volatile unsigned char __sparc32_atomic_locks[64] abort (); \ __v7_exchange_24_rel (mem, newval); }) +# define atomic_full_barrier() __asm ("" ::: "memory") +# define atomic_read_barrier() atomic_full_barrier () +# define atomic_write_barrier() atomic_full_barrier () + #else /* In libc.a/libpthread.a etc. we don't know if we'll be run on @@ -319,6 +322,35 @@ extern uint64_t _dl_hwcap __attribute__((weak)); __acev_w24ret = __v7_exchange_24_rel (mem, newval); \ __acev_w24ret; }) +#define atomic_full_barrier() \ + do { \ + if (__atomic_is_v9) \ + /* membar #LoadLoad | #LoadStore | #StoreLoad | #StoreStore */ \ + __asm __volatile (".word 0x8143e00f" : : : "memory"); \ + else \ + __asm __volatile ("" : : : "memory"); \ + } while (0) + +#define atomic_read_barrier() \ + do { \ + if (__atomic_is_v9) \ + /* membar #LoadLoad | #LoadStore */ \ + __asm __volatile (".word 0x8143e005" : : : "memory"); \ + else \ + __asm __volatile ("" : : : "memory"); \ + } while (0) + +#define atomic_write_barrier() \ + do { \ + if (__atomic_is_v9) \ + /* membar #StoreLoad | #StoreStore */ \ + __asm __volatile (".word 0x8143e00a" : : : "memory"); \ + else \ + __asm __volatile ("" : : : "memory"); \ + } while (0) + #endif +#include <sysdep.h> + #endif /* bits/atomic.h */ |