* sysdeps/x86_64/cacheinfo.c (init_cacheinfo): Work around problem

	with some Pentium Ds.

1 files changed, 8 insertions, 0 deletions

diff --git a/sysdeps/x86_64/cacheinfo.c b/sysdeps/x86_64/cacheinfo.c
index 5b92bd5849..12102fea81 100644
--- a/sysdeps/x86_64/cacheinfo.c
+++ b/sysdeps/x86_64/cacheinfo.c
@@ -456,6 +456,13 @@ init_cacheinfo (void)
               asm volatile ("cpuid"
 		            : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
 		            : "0" (4), "2" (i++));
+
+	      /* There seems to be a bug in at least some Pentium Ds
+		 which sometimes fail to iterate all cache parameters.
+		 Do not loop indefinitely here, stop in this case and
+		 assume there is no such information.  */
+	      if ((eax & 0x1f) == 0)
+		goto intel_bug_no_cache_info;
 	    }
           while (((eax >> 5) & 0x7) != level);
 
@@ -463,6 +470,7 @@ init_cacheinfo (void)
 	}
       else
         {
+	intel_bug_no_cache_info:
 	  /* Assume that all logical threads share the highest cache level.  */
           asm volatile ("cpuid"
 		        : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)