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| author | Ulrich Drepper <drepper@redhat.com> | 2009-05-10 18:38:52 +0000 |
|---|---|---|
| committer | Ulrich Drepper <drepper@redhat.com> | 2009-05-10 18:38:52 +0000 |
| commit | deb84c43b1bb0958d942e6739f136d4c11189b3b (patch) | |
| tree | 91d06939ae5470d2cbd90c3cb279316554b75302 /sysdeps | |
| parent | eb29449a9a601f535cab50068e02aee0aa1ed379 (diff) | |
| download | glibc-deb84c43b1bb0958d942e6739f136d4c11189b3b.tar.gz glibc-deb84c43b1bb0958d942e6739f136d4c11189b3b.tar.xz glibc-deb84c43b1bb0958d942e6739f136d4c11189b3b.zip | |
* version.h (VERSION): Bump to 2.10.1. cvs/fedora-glibc-20090510T1842 cvs/master
* nss/getXXbyYY_r.c: If NO_COMPAT_NEEDED is defined don't define any compatibility functions. * nss/getXXent_r.c: Likewise. * gshadow/getsgent_r.c: Define NO_COMPAT_NEEDED. * gshadow/getsgnam_r.c: Likewise. * gshadow/Version: Remove duplicate entries. * sysdeps/x86_64/cacheinfo.c (intel_02_cache_info): Add missing entries for recent processor. * sysdeps/unix/sysv/linux/i386/sysconf.c (intel_02_cache_info): Likewise.
Diffstat (limited to 'sysdeps')
| -rw-r--r-- | sysdeps/unix/sysv/linux/i386/sysconf.c | 1 | ||||
| -rw-r--r-- | sysdeps/x86_64/cacheinfo.c | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/sysdeps/unix/sysv/linux/i386/sysconf.c b/sysdeps/unix/sysv/linux/i386/sysconf.c index b1c93d7359..f59e0c3fad 100644 --- a/sysdeps/unix/sysv/linux/i386/sysconf.c +++ b/sysdeps/unix/sysv/linux/i386/sysconf.c @@ -80,6 +80,7 @@ static const struct intel_02_cache_info { 0x0a, _SC_LEVEL1_DCACHE_SIZE, 8192, 2, 32 }, { 0x0c, _SC_LEVEL1_DCACHE_SIZE, 16384, 4, 32 }, { 0x0d, _SC_LEVEL1_DCACHE_SIZE, 16384, 4, 64 }, + { 0x21, _SC_LEVEL2_CACHE_SIZE, 262144, 8, 64 }, { 0x22, _SC_LEVEL3_CACHE_SIZE, 524288, 4, 64 }, { 0x23, _SC_LEVEL3_CACHE_SIZE, 1048576, 8, 64 }, { 0x25, _SC_LEVEL3_CACHE_SIZE, 2097152, 8, 64 }, diff --git a/sysdeps/x86_64/cacheinfo.c b/sysdeps/x86_64/cacheinfo.c index 8769e9c966..1ec4ca19c9 100644 --- a/sysdeps/x86_64/cacheinfo.c +++ b/sysdeps/x86_64/cacheinfo.c @@ -42,6 +42,7 @@ static const struct intel_02_cache_info { 0x0a, _SC_LEVEL1_DCACHE_SIZE, 8192, 2, 32 }, { 0x0c, _SC_LEVEL1_DCACHE_SIZE, 16384, 4, 32 }, { 0x0d, _SC_LEVEL1_DCACHE_SIZE, 16384, 4, 64 }, + { 0x21, _SC_LEVEL2_CACHE_SIZE, 262144, 8, 64 }, { 0x22, _SC_LEVEL3_CACHE_SIZE, 524288, 4, 64 }, { 0x23, _SC_LEVEL3_CACHE_SIZE, 1048576, 8, 64 }, { 0x25, _SC_LEVEL3_CACHE_SIZE, 2097152, 8, 64 }, |