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| author | Liubov Dmitrieva <liubov.dmitrieva@intel.com> | 2013-06-28 15:28:50 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2013-06-28 15:31:40 -0700 |
| commit | 6308fd9a46a2f4aa550886e6f58190fb209ef027 (patch) | |
| tree | 668039e1091165b38354a1ffebf35b0058de3eed /sysdeps/x86_64/multiarch/strrchr.S | |
| parent | 89cd956937f46e8f4a0374994965f991642dd408 (diff) | |
| download | glibc-6308fd9a46a2f4aa550886e6f58190fb209ef027.tar.gz glibc-6308fd9a46a2f4aa550886e6f58190fb209ef027.tar.xz glibc-6308fd9a46a2f4aa550886e6f58190fb209ef027.zip | |
Skip SSE4.2 versions on Intel Silvermont
SSE2/SSSE3 versions are faster than SSE4.2 versions on Intel Silvermont.
Diffstat (limited to 'sysdeps/x86_64/multiarch/strrchr.S')
| -rw-r--r-- | sysdeps/x86_64/multiarch/strrchr.S | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/sysdeps/x86_64/multiarch/strrchr.S b/sysdeps/x86_64/multiarch/strrchr.S index ee6af6e9dd..3f92a41ef9 100644 --- a/sysdeps/x86_64/multiarch/strrchr.S +++ b/sysdeps/x86_64/multiarch/strrchr.S @@ -32,6 +32,8 @@ ENTRY(strrchr) jne 1f call __init_cpu_features 1: leaq __strrchr_sse2(%rip), %rax + testl $bit_Slow_SSE4_2, __cpu_features+CPUID_OFFSET+index_Slow_SSE4_2(%rip) + jnz 2f testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip) jz 2f leaq __strrchr_sse42(%rip), %rax |