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author | Noah Goldstein <goldstein.w.n@gmail.com> | 2022-10-14 22:00:25 -0500 |
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committer | Noah Goldstein <goldstein.w.n@gmail.com> | 2022-10-14 21:21:58 -0700 |
commit | 52ab7604db35e0421bc3d2468a3af52b2c513a7b (patch) | |
tree | 2763b19062339644b3a747ad81ca38d253bd8ce7 /sysdeps/x86_64/multiarch/memrchr-avx2-rtm.S | |
parent | 2c42257314536b94cc8d52edede86e94e98c1436 (diff) | |
download | glibc-52ab7604db35e0421bc3d2468a3af52b2c513a7b.tar.gz glibc-52ab7604db35e0421bc3d2468a3af52b2c513a7b.tar.xz glibc-52ab7604db35e0421bc3d2468a3af52b2c513a7b.zip |
x86: Update VEC macros to complete API for evex/evex512 impls
1) Copy so that backport will be easier. 2) Make section only define if there is not a previous definition 3) Add `VEC_lo` definition for proper reg-width but in the ymm/zmm0-15 range. 4) Add macros for accessing GPRs based on VEC_SIZE This is to make it easier to do think like: ``` vpcmpb %VEC(0), %VEC(1), %k0 kmov{d|q} %k0, %{eax|rax} test %{eax|rax} ``` It adds macro s.t any GPR can get the proper width with: `V{upcase_GPR_name}` and any mask insn can get the proper width with: `{upcase_mask_insn_without_postfix}` This commit does not change libc.so Tested build on x86-64
Diffstat (limited to 'sysdeps/x86_64/multiarch/memrchr-avx2-rtm.S')
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