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| author | Andrew Senkevich <andrew.senkevich@intel.com> | 2015-06-08 14:07:59 +0300 |
|---|---|---|
| committer | Andrew Senkevich <andrew.senkevich@intel.com> | 2015-06-08 14:07:59 +0300 |
| commit | 5fe2a126d115e6b3220886f416b6b544252f8589 (patch) | |
| tree | 2d0b7b7fb57135bc5885bcc0a771c9e99a52c734 /sysdeps/x86_64/multiarch/init-arch.h | |
| parent | 3ac3ff325d4042c8a8e20821195938601994d8f8 (diff) | |
| download | glibc-5fe2a126d115e6b3220886f416b6b544252f8589.tar.gz glibc-5fe2a126d115e6b3220886f416b6b544252f8589.tar.xz glibc-5fe2a126d115e6b3220886f416b6b544252f8589.zip | |
This patch adds detection of availability for AVX512F and AVX512DQ ISAs.
* sysdeps/x86_64/multiarch/init-arch.h (bit_AVX512F_Usable,
bit_AVX512DQ_Usable, bit_Opmask_state, bit_ZMM0_15_state,
bit_ZMM16_31_state): New macro.
* sysdeps/x86_64/multiarch/init-arch.c (__init_cpu_features):
Check and set bit_AVX512F_Usable, bit_AVX512DQ_Usable.
Diffstat (limited to 'sysdeps/x86_64/multiarch/init-arch.h')
| -rw-r--r-- | sysdeps/x86_64/multiarch/init-arch.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/sysdeps/x86_64/multiarch/init-arch.h b/sysdeps/x86_64/multiarch/init-arch.h index e6b5ba5530..cfc6e7049e 100644 --- a/sysdeps/x86_64/multiarch/init-arch.h +++ b/sysdeps/x86_64/multiarch/init-arch.h @@ -26,6 +26,8 @@ #define bit_Slow_SSE4_2 (1 << 9) #define bit_AVX2_Usable (1 << 10) #define bit_AVX_Fast_Unaligned_Load (1 << 11) +#define bit_AVX512F_Usable (1 << 12) +#define bit_AVX512DQ_Usable (1 << 13) /* CPUID Feature flags. */ @@ -43,10 +45,15 @@ /* COMMON_CPUID_INDEX_7. */ #define bit_RTM (1 << 11) #define bit_AVX2 (1 << 5) +#define bit_AVX512F (1 << 16) +#define bit_AVX512DQ (1 << 17) /* XCR0 Feature flags. */ #define bit_XMM_state (1 << 1) #define bit_YMM_state (2 << 1) +#define bit_Opmask_state (1 << 5) +#define bit_ZMM0_15_state (1 << 6) +#define bit_ZMM16_31_state (1 << 7) /* The integer bit array index for the first set of internal feature bits. */ # define FEATURE_INDEX_1 0 @@ -76,6 +83,8 @@ # define index_Slow_SSE4_2 FEATURE_INDEX_1*FEATURE_SIZE # define index_AVX2_Usable FEATURE_INDEX_1*FEATURE_SIZE # define index_AVX_Fast_Unaligned_Load FEATURE_INDEX_1*FEATURE_SIZE +# define index_AVX512F_Usable FEATURE_INDEX_1*FEATURE_SIZE +# define index_AVX512DQ_Usable FEATURE_INDEX_1*FEATURE_SIZE #else /* __ASSEMBLER__ */ @@ -152,6 +161,10 @@ extern const struct cpu_features *__get_cpu_features (void) HAS_CPUID_FLAG (COMMON_CPUID_INDEX_7, ebx, bit_RTM) # define CPUID_AVX2 \ HAS_CPUID_FLAG (COMMON_CPUID_INDEX_7, ebx, bit_AVX2) +# define CPUID_AVX512F \ + HAS_CPUID_FLAG (COMMON_CPUID_INDEX_7, ebx, bit_AVX512F) +# define CPUID_AVX512DQ \ + HAS_CPUID_FLAG (COMMON_CPUID_INDEX_7, ebx, bit_AVX512DQ) /* HAS_* evaluates to true if we may use the feature at runtime. */ # define HAS_SSE2 HAS_CPU_FEATURE (COMMON_CPUID_INDEX_1, edx, bit_SSE2) @@ -172,6 +185,8 @@ extern const struct cpu_features *__get_cpu_features (void) # define index_Slow_SSE4_2 FEATURE_INDEX_1 # define index_AVX2_Usable FEATURE_INDEX_1 # define index_AVX_Fast_Unaligned_Load FEATURE_INDEX_1 +# define index_AVX512F_Usable FEATURE_INDEX_1 +# define index_AVX512DQ_Usable FEATURE_INDEX_1 # define HAS_ARCH_FEATURE(name) \ ((__get_cpu_features ()->feature[index_##name] & (bit_##name)) != 0) @@ -182,6 +197,8 @@ extern const struct cpu_features *__get_cpu_features (void) # define HAS_FAST_UNALIGNED_LOAD HAS_ARCH_FEATURE (Fast_Unaligned_Load) # define HAS_AVX HAS_ARCH_FEATURE (AVX_Usable) # define HAS_AVX2 HAS_ARCH_FEATURE (AVX2_Usable) +# define HAS_AVX512F HAS_ARCH_FEATURE (AVX512F_Usable) +# define HAS_AVX512DQ HAS_ARCH_FEATURE (AVX512DQ_Usable) # define HAS_FMA HAS_ARCH_FEATURE (FMA_Usable) # define HAS_FMA4 HAS_ARCH_FEATURE (FMA4_Usable) # define HAS_AVX_FAST_UNALIGNED_LOAD HAS_ARCH_FEATURE (AVX_Fast_Unaligned_Load) |