* sysdeps/x86_64/cacheinfo.c (__x86_64_shared_cache_size): Define.

	(init_cacheinfo): Initialize it.
	* sysdeps/x86_64/memset.S: Use __x86_64_shared_cache_size.
	Always define bzero.
	Remove non-glibc code.
	* sysdeps/x86_64/bzero.S: Make an empty file.

2007-10-15  H.J. Lu  <hongjiu.lu@intel.com>

	* sysdeps/x86_64/cacheinfo.c
	(__x86_64_preferred_memory_instruction): New.
	(init_cacheinfo): Initialize __x86_64_preferred_memory_instruction.

	* sysdeps/x86_64/memset.S: Rewrite.

	* nss/getXXbyYY_r.c (REENTRANT_NAME): Mangle startp and start_fct

1 files changed, 26 insertions, 4 deletions

diff --git a/sysdeps/x86_64/cacheinfo.c b/sysdeps/x86_64/cacheinfo.c
index 12102fea81..114ec673d3 100644
--- a/sysdeps/x86_64/cacheinfo.c
+++ b/sysdeps/x86_64/cacheinfo.c
@@ -404,9 +404,20 @@ long int __x86_64_data_cache_size_half attribute_hidden = 32 * 1024 / 2;
 /* Shared cache size for use in memory and string routines, typically
    L2 or L3 size.  */
 long int __x86_64_shared_cache_size_half attribute_hidden = 1024 * 1024 / 2;
+long int __x86_64_shared_cache_size attribute_hidden = 1024 * 1024;
 /* PREFETCHW support flag for use in memory and string routines.  */
 int __x86_64_prefetchw attribute_hidden;
 
+/* Instructions preferred for memory and string routines.
+
+  0: Regular instructions
+  1: MMX instructions
+  2: SSE2 instructions
+  3: SSSE3 instructions
+
+  */
+int __x86_64_preferred_memory_instruction attribute_hidden;
+
 
 static void
 __attribute__((constructor))
@@ -444,6 +455,17 @@ init_cacheinfo (void)
           shared = handle_intel (_SC_LEVEL2_CACHE_SIZE, max_cpuid);
 	}
 
+      asm volatile ("cpuid"
+		    : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
+		    : "0" (1));
+
+      /* Intel prefers SSSE3 instructions for memory/string rountines
+	 if they are avaiable.  */
+      if ((ecx & 0x200))
+	__x86_64_preferred_memory_instruction = 3;
+      else
+	__x86_64_preferred_memory_instruction = 2;
+
       /* Figure out the number of logical threads that share the
 	 highest cache level.  */
       if (max_cpuid >= 4)
@@ -472,9 +494,6 @@ init_cacheinfo (void)
         {
 	intel_bug_no_cache_info:
 	  /* Assume that all logical threads share the highest cache level.  */
-          asm volatile ("cpuid"
-		        : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
-		        : "0" (1));
 
 	  threads = (ebx >> 16) & 0xff;
 	}
@@ -549,5 +568,8 @@ init_cacheinfo (void)
     __x86_64_data_cache_size_half = data / 2;
 
   if (shared > 0)
-    __x86_64_shared_cache_size_half = shared / 2;
+    {
+      __x86_64_shared_cache_size_half = shared / 2;
+      __x86_64_shared_cache_size = shared;
+    }
 }